/* Generated automatically by the program `genconstants'
   from the machine description file `md'.  */

#ifndef GCC_INSN_CONSTANTS_H
#define GCC_INSN_CONSTANTS_H

#define O3_REG 11
#define F0_REG 32
#define UNSPEC_PDIST 50
#define L3_REG 19
#define FCC2_REG 98
#define I3_REG 27
#define O6_REG 14
#define F3_REG 35
#define UNSPEC_TLSGD 30
#define UNSPEC_SETHH 9
#define L6_REG 22
#define F24_REG 56
#define I6_REG 30
#define UNSPEC_FEXPAND 43
#define F48_REG 80
#define F6_REG 38
#define UNSPEC_EMB_TEXTUHI 13
#define UNSPECV_PROBE_STACK_RANGE 11
#define F11_REG 43
#define UNSPEC_FHSUB 84
#define UNSPEC_MUL8SU 87
#define UNSPEC_MOVE_PIC_LABEL 5
#define UNSPEC_SETLM 10
#define F31_REG 63
#define F9_REG 41
#define UNSPEC_EDGE8 51
#define UNSPEC_CMASK16 78
#define UNSPEC_ARRAY8 57
#define F17_REG 49
#define F15_REG 47
#define G2_REG 2
#define UNSPEC_EDGE8L 52
#define F34_REG 66
#define UNSPEC_EDGE8N 70
#define UNSPEC_EDGE16L 54
#define UNSPEC_FRAME_BLOCKAGE 3
#define UNSPEC_EDGE16N 72
#define UNSPEC_MOVE_GOTDATA 19
#define F40_REG 72
#define UNSPEC_ARRAY32 59
#define UNSPEC_EDGE16 53
#define UNSPEC_MULDUL 47
#define UNSPECV_BLOCKAGE 0
#define F50_REG 82
#define F28_REG 60
#define UNSPEC_EDGE8LN 71
#define F58_REG 90
#define UNSPEC_FCMP 49
#define CC_REG 100
#define UNSPEC_SETH44 6
#define L1_REG 17
#define UNSPEC_FPACKFIX 42
#define UNSPEC_TLSIE 33
#define I1_REG 25
#define FCC3_REG 99
#define O4_REG 12
#define F10_REG 42
#define F1_REG 33
#define L2_REG 18
#define L4_REG 20
#define I4_REG 28
#define F56_REG 88
#define UNSPEC_FHADD 83
#define O7_REG 15
#define F4_REG 36
#define UNSPEC_SP_SET 60
#define FCC0_REG 96
#define L7_REG 23
#define UNSPECV_CAS 8
#define F44_REG 76
#define UNSPECV_LDSTUB 10
#define I7_REG 31
#define F2_REG 34
#define F7_REG 39
#define I2_REG 26
#define F19_REG 51
#define UNSPEC_ATOMIC 21
#define UNSPEC_EDGE32LN 75
#define UNSPEC_EMB_TEXTULO 15
#define G0_REG 0
#define SFP_REG 101
#define UNSPEC_PDISTN 81
#define F54_REG 86
#define UNSPECV_FLUSHW 1
#define UNSPEC_TLSLD_BASE 35
#define G5_REG 5
#define G3_REG 3
#define F62_REG 94
#define UNSPEC_TLSLE 34
#define UNSPEC_LOAD_PCREL_SYM 2
#define G6_REG 6
#define UNSPEC_FPACK32 41
#define F5_REG 37
#define F38_REG 70
#define F27_REG 59
#define UNSPEC_EMB_HISUM 11
#define F25_REG 57
#define UNSPEC_FPACK16 40
#define F16_REG 48
#define FCC1_REG 97
#define UNSPEC_MUL8UL 46
#define O2_REG 10
#define F46_REG 78
#define F32_REG 64
#define UNSPEC_MUL8 86
#define F42_REG 74
#define F26_REG 58
#define UNSPEC_MOVE_PIC 0
#define UNSPEC_CMASK32 79
#define UNSPEC_CMASK8 77
#define O5_REG 13
#define F23_REG 55
#define O1_REG 9
#define L5_REG 21
#define UNSPEC_ARRAY16 58
#define UNSPEC_UPDATE_RETURN 1
#define UNSPEC_SETM44 7
#define I5_REG 29
#define UNSPEC_FCHKSM16 80
#define F52_REG 84
#define UNSPEC_MULDSU 88
#define UNSPEC_EDGE32 55
#define UNSPEC_BSHUFFLE 76
#define UNSPECV_SWAP 9
#define F36_REG 68
#define F60_REG 92
#define F14_REG 46
#define F30_REG 62
#define F8_REG 40
#define F29_REG 61
#define UNSPEC_MEMBAR 20
#define UNSPEC_EDGE16LN 73
#define F22_REG 54
#define G1_REG 1
#define UNSPEC_EMB_SETHM 18
#define UNSPEC_EMB_TEXTHI 14
#define GSR_REG 102
#define F12_REG 44
#define UNSPEC_MUL16AL 45
#define UNSPEC_ALIGNDATA 48
#define F20_REG 52
#define UNSPECV_SAVEW 6
#define G4_REG 4
#define UNSPEC_TLSLDM 31
#define UNSPEC_MUL16AU 44
#define UNSPEC_TLSLDO 32
#define UNSPEC_EDGE32L 56
#define UNSPEC_XMUL 85
#define UNSPEC_EDGE32N 74
#define F18_REG 50
#define O0_REG 8
#define G7_REG 7
#define L0_REG 16
#define F21_REG 53
#define UNSPECV_FLUSH 4
#define UNSPEC_FUCMP 82
#define I0_REG 24
#define F13_REG 45
#define UNSPEC_SP_TEST 61

#endif /* GCC_INSN_CONSTANTS_H */
