/* Generated automatically by the program `gencodes'
   from the machine description file `md'.  */

#ifndef GCC_INSN_CODES_H
#define GCC_INSN_CODES_H

enum insn_code {
  CODE_FOR_nothing = 0,

  CODE_FOR_x86_fnstsw_1 = 47,
  CODE_FOR_x86_sahf_1 = 48,
  CODE_FOR_kmovw = 91,
  CODE_FOR_movsi_insv_1 = 118,
  CODE_FOR_movdi_insv_1 = 119,
  CODE_FOR_swapxf = 130,
  CODE_FOR_zero_extendqidi2 = 134,
  CODE_FOR_zero_extendhidi2 = 135,
  CODE_FOR_zero_extendqisi2_and = 136,
  CODE_FOR_zero_extendhisi2_and = 137,
  CODE_FOR_zero_extendqihi2_and = 140,
  CODE_FOR_extendsidi2_1 = 143,
  CODE_FOR_extendqidi2 = 144,
  CODE_FOR_extendhidi2 = 145,
  CODE_FOR_extendhisi2 = 146,
  CODE_FOR_extendqisi2 = 148,
  CODE_FOR_extendqihi2 = 150,
  CODE_FOR_truncxfsf2_i387_noop = 164,
  CODE_FOR_truncxfdf2_i387_noop = 165,
  CODE_FOR_fix_truncsfsi_sse = 170,
  CODE_FOR_fix_truncsfdi_sse = 171,
  CODE_FOR_fix_truncdfsi_sse = 172,
  CODE_FOR_fix_truncdfdi_sse = 173,
  CODE_FOR_fix_trunchi_fisttp_i387_1 = 174,
  CODE_FOR_fix_truncsi_fisttp_i387_1 = 175,
  CODE_FOR_fix_truncdi_fisttp_i387_1 = 176,
  CODE_FOR_fix_trunchi_i387_fisttp = 177,
  CODE_FOR_fix_truncsi_i387_fisttp = 178,
  CODE_FOR_fix_truncdi_i387_fisttp = 179,
  CODE_FOR_fix_trunchi_i387_fisttp_with_temp = 180,
  CODE_FOR_fix_truncsi_i387_fisttp_with_temp = 181,
  CODE_FOR_fix_truncdi_i387_fisttp_with_temp = 182,
  CODE_FOR_fix_truncdi_i387 = 186,
  CODE_FOR_fix_truncdi_i387_with_temp = 187,
  CODE_FOR_fix_trunchi_i387 = 188,
  CODE_FOR_fix_truncsi_i387 = 189,
  CODE_FOR_fix_trunchi_i387_with_temp = 190,
  CODE_FOR_fix_truncsi_i387_with_temp = 191,
  CODE_FOR_x86_fnstcw_1 = 192,
  CODE_FOR_x86_fldcw_1 = 193,
  CODE_FOR_floathisf2 = 194,
  CODE_FOR_floathidf2 = 195,
  CODE_FOR_floathixf2 = 196,
  CODE_FOR_floatsixf2 = 197,
  CODE_FOR_floatdixf2 = 198,
  CODE_FOR_floatdisf2_i387_with_xmm = 207,
  CODE_FOR_floatdidf2_i387_with_xmm = 208,
  CODE_FOR_floatdixf2_i387_with_xmm = 209,
  CODE_FOR_addqi3_cc = 219,
  CODE_FOR_addsi_1_zext = 222,
  CODE_FOR_addqi_ext_1 = 244,
  CODE_FOR_adcxsi3 = 295,
  CODE_FOR_adcxdi3 = 296,
  CODE_FOR_divmodsi4_1 = 335,
  CODE_FOR_divmoddi4_1 = 336,
  CODE_FOR_divmodhiqi3 = 343,
  CODE_FOR_udivmodsi4_1 = 344,
  CODE_FOR_udivmoddi4_1 = 345,
  CODE_FOR_udivmodhiqi3 = 352,
  CODE_FOR_kandnqi = 375,
  CODE_FOR_kandnhi = 376,
  CODE_FOR_andqi_ext_0 = 384,
  CODE_FOR_kxnorqi = 410,
  CODE_FOR_kxnorhi = 411,
  CODE_FOR_kortestzhi = 412,
  CODE_FOR_kortestchi = 413,
  CODE_FOR_kunpckhi = 414,
  CODE_FOR_copysignsf3_const = 472,
  CODE_FOR_copysigndf3_const = 473,
  CODE_FOR_copysigntf3_const = 474,
  CODE_FOR_copysignsf3_var = 475,
  CODE_FOR_copysigndf3_var = 476,
  CODE_FOR_copysigntf3_var = 477,
  CODE_FOR_x86_64_shld = 490,
  CODE_FOR_x86_shld = 491,
  CODE_FOR_x86_64_shrd = 520,
  CODE_FOR_x86_shrd = 521,
  CODE_FOR_ashrdi3_cvt = 522,
  CODE_FOR_ashrsi3_cvt = 523,
  CODE_FOR_ix86_rotldi3_doubleword = 565,
  CODE_FOR_ix86_rotlti3_doubleword = 566,
  CODE_FOR_ix86_rotrdi3_doubleword = 567,
  CODE_FOR_ix86_rotrti3_doubleword = 568,
  CODE_FOR_setcc_sf_sse = 594,
  CODE_FOR_setcc_df_sse = 595,
  CODE_FOR_jump = 636,
  CODE_FOR_blockage = 655,
  CODE_FOR_prologue_use = 657,
  CODE_FOR_simple_return_internal = 658,
  CODE_FOR_simple_return_internal_long = 659,
  CODE_FOR_simple_return_pop_internal = 660,
  CODE_FOR_simple_return_indirect_internal = 661,
  CODE_FOR_nop = 662,
  CODE_FOR_nops = 663,
  CODE_FOR_pad = 664,
  CODE_FOR_set_got = 665,
  CODE_FOR_set_got_labelled = 666,
  CODE_FOR_set_got_rex64 = 667,
  CODE_FOR_set_rip_rex64 = 668,
  CODE_FOR_set_got_offset_rex64 = 669,
  CODE_FOR_eh_return_internal = 670,
  CODE_FOR_leave = 671,
  CODE_FOR_leave_rex64 = 672,
  CODE_FOR_split_stack_return = 673,
  CODE_FOR_ffssi2_no_cmove = 674,
  CODE_FOR_ctzhi2 = 679,
  CODE_FOR_ctzsi2 = 680,
  CODE_FOR_ctzdi2 = 681,
  CODE_FOR_clzhi2_lzcnt = 682,
  CODE_FOR_clzsi2_lzcnt = 683,
  CODE_FOR_clzdi2_lzcnt = 684,
  CODE_FOR_bmi_bextr_si = 687,
  CODE_FOR_bmi_bextr_di = 688,
  CODE_FOR_bmi2_bzhi_si3 = 695,
  CODE_FOR_bmi2_bzhi_di3 = 696,
  CODE_FOR_bmi2_pdep_si3 = 697,
  CODE_FOR_bmi2_pdep_di3 = 698,
  CODE_FOR_bmi2_pext_si3 = 699,
  CODE_FOR_bmi2_pext_di3 = 700,
  CODE_FOR_tbm_bextri_si = 701,
  CODE_FOR_tbm_bextri_di = 702,
  CODE_FOR_bsr_rex64 = 721,
  CODE_FOR_bsr = 722,
  CODE_FOR_popcounthi2 = 724,
  CODE_FOR_popcountsi2 = 725,
  CODE_FOR_popcountdi2 = 726,
  CODE_FOR_bswaphi_lowpart = 736,
  CODE_FOR_paritydi2_cmp = 737,
  CODE_FOR_paritysi2_cmp = 738,
#define CODE_FOR_tls_initial_exec_64_sun CODE_FOR_nothing
  CODE_FOR_truncxfsf2_i387_noop_unspec = 799,
  CODE_FOR_truncxfdf2_i387_noop_unspec = 800,
  CODE_FOR_sqrtxf2 = 801,
  CODE_FOR_sqrt_extendsfxf2_i387 = 802,
  CODE_FOR_sqrt_extenddfxf2_i387 = 803,
  CODE_FOR_fpremxf4_i387 = 807,
  CODE_FOR_fprem1xf4_i387 = 808,
  CODE_FOR_sincosxf3 = 815,
  CODE_FOR_sincos_extendsfxf3_i387 = 816,
  CODE_FOR_sincos_extenddfxf3_i387 = 817,
  CODE_FOR_fptanxf4_i387 = 818,
  CODE_FOR_fptan_extendsfxf4_i387 = 819,
  CODE_FOR_fptan_extenddfxf4_i387 = 820,
  CODE_FOR_fpatan_extendsfxf3_i387 = 822,
  CODE_FOR_fpatan_extenddfxf3_i387 = 823,
  CODE_FOR_fyl2xxf3_i387 = 824,
  CODE_FOR_fyl2x_extendsfxf3_i387 = 825,
  CODE_FOR_fyl2x_extenddfxf3_i387 = 826,
  CODE_FOR_fyl2xp1xf3_i387 = 827,
  CODE_FOR_fyl2xp1_extendsfxf3_i387 = 828,
  CODE_FOR_fyl2xp1_extenddfxf3_i387 = 829,
  CODE_FOR_fxtractxf3_i387 = 830,
  CODE_FOR_fxtract_extendsfxf3_i387 = 831,
  CODE_FOR_fxtract_extenddfxf3_i387 = 832,
  CODE_FOR_fscalexf4_i387 = 834,
  CODE_FOR_sse4_1_roundsf2 = 835,
  CODE_FOR_sse4_1_rounddf2 = 836,
  CODE_FOR_rintxf2 = 837,
  CODE_FOR_fistdi2 = 839,
  CODE_FOR_fistdi2_with_temp = 840,
  CODE_FOR_fisthi2 = 843,
  CODE_FOR_fistsi2 = 844,
  CODE_FOR_fisthi2_with_temp = 845,
  CODE_FOR_fistsi2_with_temp = 846,
  CODE_FOR_frndintxf2_floor = 847,
  CODE_FOR_frndintxf2_ceil = 848,
  CODE_FOR_frndintxf2_trunc = 849,
  CODE_FOR_frndintxf2_floor_i387 = 850,
  CODE_FOR_frndintxf2_ceil_i387 = 851,
  CODE_FOR_frndintxf2_trunc_i387 = 852,
  CODE_FOR_frndintxf2_mask_pm = 853,
  CODE_FOR_frndintxf2_mask_pm_i387 = 854,
  CODE_FOR_fistdi2_floor = 861,
  CODE_FOR_fistdi2_ceil = 862,
  CODE_FOR_fistdi2_floor_with_temp = 863,
  CODE_FOR_fistdi2_ceil_with_temp = 864,
  CODE_FOR_fisthi2_floor = 865,
  CODE_FOR_fisthi2_ceil = 866,
  CODE_FOR_fistsi2_floor = 867,
  CODE_FOR_fistsi2_ceil = 868,
  CODE_FOR_fisthi2_floor_with_temp = 869,
  CODE_FOR_fisthi2_ceil_with_temp = 870,
  CODE_FOR_fistsi2_floor_with_temp = 871,
  CODE_FOR_fistsi2_ceil_with_temp = 872,
  CODE_FOR_fxamsf2_i387 = 873,
  CODE_FOR_fxamdf2_i387 = 874,
  CODE_FOR_fxamxf2_i387 = 875,
  CODE_FOR_fxamsf2_i387_with_temp = 876,
  CODE_FOR_fxamdf2_i387_with_temp = 877,
  CODE_FOR_movmsk_df = 878,
  CODE_FOR_cld = 879,
  CODE_FOR_smaxsf3 = 929,
  CODE_FOR_sminsf3 = 930,
  CODE_FOR_smaxdf3 = 931,
  CODE_FOR_smindf3 = 932,
  CODE_FOR_pro_epilogue_adjust_stack_si_add = 937,
  CODE_FOR_pro_epilogue_adjust_stack_di_add = 938,
  CODE_FOR_pro_epilogue_adjust_stack_si_sub = 939,
  CODE_FOR_pro_epilogue_adjust_stack_di_sub = 940,
  CODE_FOR_allocate_stack_worker_probe_si = 941,
  CODE_FOR_allocate_stack_worker_probe_di = 942,
  CODE_FOR_adjust_stack_and_probesi = 943,
  CODE_FOR_adjust_stack_and_probedi = 944,
  CODE_FOR_probe_stack_rangesi = 945,
  CODE_FOR_probe_stack_rangedi = 946,
#define CODE_FOR_nonlocal_goto_receiver CODE_FOR_nothing
  CODE_FOR_trap = 947,
  CODE_FOR_stack_protect_set_si = 952,
  CODE_FOR_stack_protect_set_di = 953,
  CODE_FOR_stack_tls_protect_set_si = 954,
  CODE_FOR_stack_tls_protect_set_di = 955,
  CODE_FOR_stack_protect_test_si = 956,
  CODE_FOR_stack_protect_test_di = 957,
  CODE_FOR_stack_tls_protect_test_si = 958,
  CODE_FOR_stack_tls_protect_test_di = 959,
  CODE_FOR_sse4_2_crc32qi = 960,
  CODE_FOR_sse4_2_crc32hi = 961,
  CODE_FOR_sse4_2_crc32si = 962,
  CODE_FOR_sse4_2_crc32di = 963,
  CODE_FOR_rdpmc = 964,
  CODE_FOR_rdpmc_rex64 = 965,
  CODE_FOR_rdtsc = 966,
  CODE_FOR_rdtsc_rex64 = 967,
  CODE_FOR_rdtscp = 968,
  CODE_FOR_rdtscp_rex64 = 969,
  CODE_FOR_fxsave = 970,
  CODE_FOR_fxsave64 = 971,
  CODE_FOR_fxrstor = 972,
  CODE_FOR_fxrstor64 = 973,
  CODE_FOR_xsave = 974,
  CODE_FOR_xsaveopt = 975,
  CODE_FOR_xsave_rex64 = 976,
  CODE_FOR_xsaveopt_rex64 = 977,
  CODE_FOR_xsave64 = 978,
  CODE_FOR_xsaveopt64 = 979,
  CODE_FOR_xrstor = 980,
  CODE_FOR_xrstor_rex64 = 981,
  CODE_FOR_xrstor64 = 982,
  CODE_FOR_fnstenv = 983,
  CODE_FOR_fldenv = 984,
  CODE_FOR_fnstsw = 985,
  CODE_FOR_fnclex = 986,
  CODE_FOR_lwp_slwpcbsi = 989,
  CODE_FOR_lwp_slwpcbdi = 990,
  CODE_FOR_rdfsbasesi = 995,
  CODE_FOR_rdgsbasesi = 996,
  CODE_FOR_rdfsbasedi = 997,
  CODE_FOR_rdgsbasedi = 998,
  CODE_FOR_wrfsbasesi = 999,
  CODE_FOR_wrgsbasesi = 1000,
  CODE_FOR_wrfsbasedi = 1001,
  CODE_FOR_wrgsbasedi = 1002,
  CODE_FOR_rdrandhi_1 = 1003,
  CODE_FOR_rdrandsi_1 = 1004,
  CODE_FOR_rdranddi_1 = 1005,
  CODE_FOR_rdseedhi_1 = 1006,
  CODE_FOR_rdseedsi_1 = 1007,
  CODE_FOR_rdseeddi_1 = 1008,
  CODE_FOR_xbegin_1 = 1010,
  CODE_FOR_xend = 1011,
  CODE_FOR_xabort = 1012,
  CODE_FOR_xtest_1 = 1013,
  CODE_FOR_sse_movntq = 1019,
  CODE_FOR_mmx_rcpv2sf2 = 1027,
  CODE_FOR_mmx_rcpit1v2sf3 = 1028,
  CODE_FOR_mmx_rcpit2v2sf3 = 1029,
  CODE_FOR_mmx_rsqrtv2sf2 = 1030,
  CODE_FOR_mmx_rsqit1v2sf3 = 1031,
  CODE_FOR_mmx_haddv2sf3 = 1032,
  CODE_FOR_mmx_hsubv2sf3 = 1033,
  CODE_FOR_mmx_addsubv2sf3 = 1034,
  CODE_FOR_mmx_gtv2sf3 = 1036,
  CODE_FOR_mmx_gev2sf3 = 1037,
  CODE_FOR_mmx_pf2id = 1038,
  CODE_FOR_mmx_pf2iw = 1039,
  CODE_FOR_mmx_pi2fw = 1040,
  CODE_FOR_mmx_floatv2si2 = 1041,
  CODE_FOR_mmx_pswapdv2sf2 = 1042,
  CODE_FOR_mmx_ashrv4hi3 = 1073,
  CODE_FOR_mmx_ashrv2si3 = 1074,
  CODE_FOR_mmx_ashlv4hi3 = 1075,
  CODE_FOR_mmx_lshrv4hi3 = 1076,
  CODE_FOR_mmx_ashlv2si3 = 1077,
  CODE_FOR_mmx_lshrv2si3 = 1078,
  CODE_FOR_mmx_ashlv1di3 = 1079,
  CODE_FOR_mmx_lshrv1di3 = 1080,
  CODE_FOR_mmx_gtv8qi3 = 1084,
  CODE_FOR_mmx_gtv4hi3 = 1085,
  CODE_FOR_mmx_gtv2si3 = 1086,
  CODE_FOR_mmx_andnotv8qi3 = 1087,
  CODE_FOR_mmx_andnotv4hi3 = 1088,
  CODE_FOR_mmx_andnotv2si3 = 1089,
  CODE_FOR_mmx_packsswb = 1099,
  CODE_FOR_mmx_packssdw = 1100,
  CODE_FOR_mmx_packuswb = 1101,
  CODE_FOR_mmx_punpckhbw = 1102,
  CODE_FOR_mmx_punpcklbw = 1103,
  CODE_FOR_mmx_punpckhwd = 1104,
  CODE_FOR_mmx_punpcklwd = 1105,
  CODE_FOR_mmx_punpckhdq = 1106,
  CODE_FOR_mmx_punpckldq = 1107,
  CODE_FOR_mmx_pextrw = 1109,
  CODE_FOR_mmx_pshufw_1 = 1110,
  CODE_FOR_mmx_pswapdv2si2 = 1111,
  CODE_FOR_mmx_psadbw = 1120,
  CODE_FOR_mmx_pmovmskb = 1121,
  CODE_FOR_avx512f_loadv16si_mask = 1146,
  CODE_FOR_avx512f_loadv16sf_mask = 1147,
  CODE_FOR_avx512f_loadv8di_mask = 1148,
  CODE_FOR_avx512f_loadv8df_mask = 1149,
  CODE_FOR_avx512f_blendmv16si = 1150,
  CODE_FOR_avx512f_blendmv16sf = 1151,
  CODE_FOR_avx512f_blendmv8di = 1152,
  CODE_FOR_avx512f_blendmv8df = 1153,
  CODE_FOR_avx512f_storev16si_mask = 1154,
  CODE_FOR_avx512f_storev16sf_mask = 1155,
  CODE_FOR_avx512f_storev8di_mask = 1156,
  CODE_FOR_avx512f_storev8df_mask = 1157,
  CODE_FOR_sse2_movq128 = 1158,
  CODE_FOR_movdi_to_sse = 1159,
  CODE_FOR_avx512f_storeups512 = 1168,
  CODE_FOR_avx_storeups256 = 1169,
  CODE_FOR_sse_storeups = 1170,
  CODE_FOR_avx512f_storeupd512 = 1171,
  CODE_FOR_avx_storeupd256 = 1172,
  CODE_FOR_sse2_storeupd = 1173,
  CODE_FOR_avx512f_storeups512_mask = 1174,
  CODE_FOR_avx512f_storeupd512_mask = 1175,
  CODE_FOR_avx_storedquv32qi = 1182,
  CODE_FOR_sse2_storedquv16qi = 1183,
  CODE_FOR_avx512f_storedquv16si = 1184,
  CODE_FOR_avx512f_storedquv8di = 1185,
  CODE_FOR_avx512f_storedquv16si_mask = 1186,
  CODE_FOR_avx512f_storedquv8di_mask = 1187,
  CODE_FOR_avx_lddqu256 = 1188,
  CODE_FOR_sse3_lddqu = 1189,
  CODE_FOR_sse2_movntisi = 1190,
  CODE_FOR_sse2_movntidi = 1191,
  CODE_FOR_avx512f_movntv16sf = 1192,
  CODE_FOR_avx_movntv8sf = 1193,
  CODE_FOR_sse_movntv4sf = 1194,
  CODE_FOR_avx512f_movntv8df = 1195,
  CODE_FOR_avx_movntv4df = 1196,
  CODE_FOR_sse2_movntv2df = 1197,
  CODE_FOR_avx512f_movntv8di = 1198,
  CODE_FOR_avx_movntv4di = 1199,
  CODE_FOR_sse2_movntv2di = 1200,
  CODE_FOR_sse_vmaddv4sf3 = 1255,
  CODE_FOR_sse_vmaddv4sf3_round = 1256,
  CODE_FOR_sse_vmsubv4sf3 = 1257,
  CODE_FOR_sse_vmsubv4sf3_round = 1258,
  CODE_FOR_sse2_vmaddv2df3 = 1259,
  CODE_FOR_sse2_vmaddv2df3_round = 1260,
  CODE_FOR_sse2_vmsubv2df3 = 1261,
  CODE_FOR_sse2_vmsubv2df3_round = 1262,
  CODE_FOR_sse_vmmulv4sf3 = 1287,
  CODE_FOR_sse_vmmulv4sf3_round = 1288,
  CODE_FOR_sse_vmdivv4sf3 = 1289,
  CODE_FOR_sse_vmdivv4sf3_round = 1290,
  CODE_FOR_sse2_vmmulv2df3 = 1291,
  CODE_FOR_sse2_vmmulv2df3_round = 1292,
  CODE_FOR_sse2_vmdivv2df3 = 1293,
  CODE_FOR_sse2_vmdivv2df3_round = 1294,
  CODE_FOR_avx512f_divv16sf3 = 1295,
  CODE_FOR_avx512f_divv16sf3_round = 1296,
  CODE_FOR_avx512f_divv16sf3_mask = 1297,
  CODE_FOR_avx512f_divv16sf3_mask_round = 1298,
  CODE_FOR_avx_divv8sf3 = 1299,
#define CODE_FOR_avx_divv8sf3_round CODE_FOR_nothing
#define CODE_FOR_avx_divv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_avx_divv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_sse_divv4sf3 = 1300,
#define CODE_FOR_sse_divv4sf3_round CODE_FOR_nothing
#define CODE_FOR_sse_divv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_sse_divv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_divv8df3 = 1301,
  CODE_FOR_avx512f_divv8df3_round = 1302,
  CODE_FOR_avx512f_divv8df3_mask = 1303,
  CODE_FOR_avx512f_divv8df3_mask_round = 1304,
  CODE_FOR_avx_divv4df3 = 1305,
#define CODE_FOR_avx_divv4df3_round CODE_FOR_nothing
#define CODE_FOR_avx_divv4df3_mask CODE_FOR_nothing
#define CODE_FOR_avx_divv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_sse2_divv2df3 = 1306,
#define CODE_FOR_sse2_divv2df3_round CODE_FOR_nothing
#define CODE_FOR_sse2_divv2df3_mask CODE_FOR_nothing
#define CODE_FOR_sse2_divv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_avx_rcpv8sf2 = 1307,
  CODE_FOR_sse_rcpv4sf2 = 1308,
  CODE_FOR_sse_vmrcpv4sf2 = 1309,
  CODE_FOR_rcp14v16sf_mask = 1311,
  CODE_FOR_rcp14v8df_mask = 1313,
  CODE_FOR_srcp14v4sf = 1314,
  CODE_FOR_srcp14v2df = 1315,
  CODE_FOR_avx512f_sqrtv16sf2 = 1316,
  CODE_FOR_avx512f_sqrtv16sf2_round = 1317,
  CODE_FOR_avx512f_sqrtv16sf2_mask = 1318,
  CODE_FOR_avx512f_sqrtv16sf2_mask_round = 1319,
  CODE_FOR_avx_sqrtv8sf2 = 1320,
#define CODE_FOR_avx_sqrtv8sf2_round CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv8sf2_mask CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv8sf2_mask_round CODE_FOR_nothing
  CODE_FOR_sse_sqrtv4sf2 = 1321,
#define CODE_FOR_sse_sqrtv4sf2_round CODE_FOR_nothing
#define CODE_FOR_sse_sqrtv4sf2_mask CODE_FOR_nothing
#define CODE_FOR_sse_sqrtv4sf2_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_sqrtv8df2 = 1322,
  CODE_FOR_avx512f_sqrtv8df2_round = 1323,
  CODE_FOR_avx512f_sqrtv8df2_mask = 1324,
  CODE_FOR_avx512f_sqrtv8df2_mask_round = 1325,
  CODE_FOR_avx_sqrtv4df2 = 1326,
#define CODE_FOR_avx_sqrtv4df2_round CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv4df2_mask CODE_FOR_nothing
#define CODE_FOR_avx_sqrtv4df2_mask_round CODE_FOR_nothing
  CODE_FOR_sse2_sqrtv2df2 = 1327,
#define CODE_FOR_sse2_sqrtv2df2_round CODE_FOR_nothing
#define CODE_FOR_sse2_sqrtv2df2_mask CODE_FOR_nothing
#define CODE_FOR_sse2_sqrtv2df2_mask_round CODE_FOR_nothing
  CODE_FOR_sse_vmsqrtv4sf2 = 1328,
  CODE_FOR_sse_vmsqrtv4sf2_round = 1329,
  CODE_FOR_sse2_vmsqrtv2df2 = 1330,
  CODE_FOR_sse2_vmsqrtv2df2_round = 1331,
  CODE_FOR_avx_rsqrtv8sf2 = 1332,
  CODE_FOR_sse_rsqrtv4sf2 = 1333,
  CODE_FOR_rsqrt14v16sf_mask = 1335,
  CODE_FOR_rsqrt14v8df_mask = 1337,
  CODE_FOR_rsqrt14v4sf = 1338,
  CODE_FOR_rsqrt14v2df = 1339,
  CODE_FOR_sse_vmrsqrtv4sf2 = 1340,
  CODE_FOR_sse_vmsmaxv4sf3 = 1413,
  CODE_FOR_sse_vmsmaxv4sf3_round = 1414,
  CODE_FOR_sse_vmsminv4sf3 = 1415,
  CODE_FOR_sse_vmsminv4sf3_round = 1416,
  CODE_FOR_sse2_vmsmaxv2df3 = 1417,
  CODE_FOR_sse2_vmsmaxv2df3_round = 1418,
  CODE_FOR_sse2_vmsminv2df3 = 1419,
  CODE_FOR_sse2_vmsminv2df3_round = 1420,
  CODE_FOR_avx_addsubv4df3 = 1433,
  CODE_FOR_sse3_addsubv2df3 = 1434,
  CODE_FOR_avx_addsubv8sf3 = 1435,
  CODE_FOR_sse3_addsubv4sf3 = 1436,
  CODE_FOR_avx_haddv4df3 = 1437,
  CODE_FOR_avx_hsubv4df3 = 1438,
  CODE_FOR_sse3_hsubv2df3 = 1440,
  CODE_FOR_avx_haddv8sf3 = 1443,
  CODE_FOR_avx_hsubv8sf3 = 1444,
  CODE_FOR_sse3_haddv4sf3 = 1445,
  CODE_FOR_sse3_hsubv4sf3 = 1446,
  CODE_FOR_avx_cmpv8sf3 = 1447,
  CODE_FOR_avx_cmpv4sf3 = 1448,
  CODE_FOR_avx_cmpv4df3 = 1449,
  CODE_FOR_avx_cmpv2df3 = 1450,
  CODE_FOR_avx_vmcmpv4sf3 = 1451,
  CODE_FOR_avx_vmcmpv2df3 = 1452,
  CODE_FOR_avx_maskcmpv8sf3 = 1457,
  CODE_FOR_sse_maskcmpv4sf3 = 1458,
  CODE_FOR_avx_maskcmpv4df3 = 1459,
  CODE_FOR_sse2_maskcmpv2df3 = 1460,
  CODE_FOR_sse_vmmaskcmpv4sf3 = 1461,
  CODE_FOR_sse2_vmmaskcmpv2df3 = 1462,
  CODE_FOR_avx512f_cmpv16si3 = 1463,
  CODE_FOR_avx512f_cmpv16si3_mask = 1464,
#define CODE_FOR_avx512f_cmpv16si3_round CODE_FOR_nothing
#define CODE_FOR_avx512f_cmpv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_cmpv16sf3 = 1465,
  CODE_FOR_avx512f_cmpv16sf3_mask = 1466,
  CODE_FOR_avx512f_cmpv16sf3_round = 1467,
  CODE_FOR_avx512f_cmpv16sf3_mask_round = 1468,
  CODE_FOR_avx512f_cmpv8di3 = 1469,
  CODE_FOR_avx512f_cmpv8di3_mask = 1470,
#define CODE_FOR_avx512f_cmpv8di3_round CODE_FOR_nothing
#define CODE_FOR_avx512f_cmpv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_avx512f_cmpv8df3 = 1471,
  CODE_FOR_avx512f_cmpv8df3_mask = 1472,
  CODE_FOR_avx512f_cmpv8df3_round = 1473,
  CODE_FOR_avx512f_cmpv8df3_mask_round = 1474,
  CODE_FOR_avx512f_ucmpv16si3 = 1475,
  CODE_FOR_avx512f_ucmpv16si3_mask = 1476,
  CODE_FOR_avx512f_ucmpv8di3 = 1477,
  CODE_FOR_avx512f_ucmpv8di3_mask = 1478,
  CODE_FOR_avx512f_vmcmpv4sf3 = 1479,
  CODE_FOR_avx512f_vmcmpv4sf3_round = 1480,
  CODE_FOR_avx512f_vmcmpv2df3 = 1481,
  CODE_FOR_avx512f_vmcmpv2df3_round = 1482,
  CODE_FOR_avx512f_vmcmpv4sf3_mask = 1483,
  CODE_FOR_avx512f_vmcmpv4sf3_mask_round = 1484,
  CODE_FOR_avx512f_vmcmpv2df3_mask = 1485,
  CODE_FOR_avx512f_vmcmpv2df3_mask_round = 1486,
  CODE_FOR_avx512f_maskcmpv16sf3 = 1487,
  CODE_FOR_avx512f_maskcmpv8sf3 = 1488,
  CODE_FOR_avx512f_maskcmpv4sf3 = 1489,
  CODE_FOR_avx512f_maskcmpv8df3 = 1490,
  CODE_FOR_avx512f_maskcmpv4df3 = 1491,
  CODE_FOR_avx512f_maskcmpv2df3 = 1492,
  CODE_FOR_sse_comi = 1493,
  CODE_FOR_sse_comi_round = 1494,
  CODE_FOR_sse2_comi = 1495,
  CODE_FOR_sse2_comi_round = 1496,
  CODE_FOR_sse_ucomi = 1497,
  CODE_FOR_sse_ucomi_round = 1498,
  CODE_FOR_sse2_ucomi = 1499,
  CODE_FOR_sse2_ucomi_round = 1500,
  CODE_FOR_avx512f_andnotv16sf3 = 1501,
  CODE_FOR_avx_andnotv8sf3 = 1502,
  CODE_FOR_sse_andnotv4sf3 = 1503,
  CODE_FOR_avx512f_andnotv8df3 = 1504,
  CODE_FOR_avx_andnotv4df3 = 1505,
  CODE_FOR_sse2_andnotv2df3 = 1506,
  CODE_FOR_avx512f_andv16sf = 1537,
  CODE_FOR_avx512f_xorv16sf = 1538,
  CODE_FOR_avx512f_andv8df = 1539,
  CODE_FOR_avx512f_xorv8df = 1540,
#define CODE_FOR_fma_fmadd_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmadd_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmadd_v16sf_maskz_1 = 1549,
  CODE_FOR_fma_fmadd_v16sf_maskz_1_round = 1550,
  CODE_FOR_fma_fmadd_v8df_maskz_1 = 1553,
  CODE_FOR_fma_fmadd_v8df_maskz_1_round = 1554,
  CODE_FOR_avx512f_fmadd_v16sf_mask = 1555,
  CODE_FOR_avx512f_fmadd_v16sf_mask_round = 1556,
  CODE_FOR_avx512f_fmadd_v8df_mask = 1557,
  CODE_FOR_avx512f_fmadd_v8df_mask_round = 1558,
  CODE_FOR_avx512f_fmadd_v16sf_mask3 = 1559,
  CODE_FOR_avx512f_fmadd_v16sf_mask3_round = 1560,
  CODE_FOR_avx512f_fmadd_v8df_mask3 = 1561,
  CODE_FOR_avx512f_fmadd_v8df_mask3_round = 1562,
#define CODE_FOR_fma_fmsub_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsub_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmsub_v16sf_maskz_1 = 1571,
  CODE_FOR_fma_fmsub_v16sf_maskz_1_round = 1572,
  CODE_FOR_fma_fmsub_v8df_maskz_1 = 1575,
  CODE_FOR_fma_fmsub_v8df_maskz_1_round = 1576,
  CODE_FOR_avx512f_fmsub_v16sf_mask = 1577,
  CODE_FOR_avx512f_fmsub_v16sf_mask_round = 1578,
  CODE_FOR_avx512f_fmsub_v8df_mask = 1579,
  CODE_FOR_avx512f_fmsub_v8df_mask_round = 1580,
  CODE_FOR_avx512f_fmsub_v16sf_mask3 = 1581,
  CODE_FOR_avx512f_fmsub_v16sf_mask3_round = 1582,
  CODE_FOR_avx512f_fmsub_v8df_mask3 = 1583,
  CODE_FOR_avx512f_fmsub_v8df_mask3_round = 1584,
#define CODE_FOR_fma_fnmadd_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmadd_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fnmadd_v16sf_maskz_1 = 1593,
  CODE_FOR_fma_fnmadd_v16sf_maskz_1_round = 1594,
  CODE_FOR_fma_fnmadd_v8df_maskz_1 = 1597,
  CODE_FOR_fma_fnmadd_v8df_maskz_1_round = 1598,
  CODE_FOR_avx512f_fnmadd_v16sf_mask = 1599,
  CODE_FOR_avx512f_fnmadd_v16sf_mask_round = 1600,
  CODE_FOR_avx512f_fnmadd_v8df_mask = 1601,
  CODE_FOR_avx512f_fnmadd_v8df_mask_round = 1602,
  CODE_FOR_avx512f_fnmadd_v16sf_mask3 = 1603,
  CODE_FOR_avx512f_fnmadd_v16sf_mask3_round = 1604,
  CODE_FOR_avx512f_fnmadd_v8df_mask3 = 1605,
  CODE_FOR_avx512f_fnmadd_v8df_mask3_round = 1606,
#define CODE_FOR_fma_fnmsub_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v2df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fnmsub_v4df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fnmsub_v16sf_maskz_1 = 1615,
  CODE_FOR_fma_fnmsub_v16sf_maskz_1_round = 1616,
  CODE_FOR_fma_fnmsub_v8df_maskz_1 = 1619,
  CODE_FOR_fma_fnmsub_v8df_maskz_1_round = 1620,
  CODE_FOR_avx512f_fnmsub_v16sf_mask = 1621,
  CODE_FOR_avx512f_fnmsub_v16sf_mask_round = 1622,
  CODE_FOR_avx512f_fnmsub_v8df_mask = 1623,
  CODE_FOR_avx512f_fnmsub_v8df_mask_round = 1624,
  CODE_FOR_avx512f_fnmsub_v16sf_mask3 = 1625,
  CODE_FOR_avx512f_fnmsub_v16sf_mask3_round = 1626,
  CODE_FOR_avx512f_fnmsub_v8df_mask3 = 1627,
  CODE_FOR_avx512f_fnmsub_v8df_mask3_round = 1628,
#define CODE_FOR_fma_fmaddsub_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v4df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmaddsub_v2df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmaddsub_v16sf_maskz_1 = 1635,
  CODE_FOR_fma_fmaddsub_v16sf_maskz_1_round = 1636,
  CODE_FOR_fma_fmaddsub_v8df_maskz_1 = 1639,
  CODE_FOR_fma_fmaddsub_v8df_maskz_1_round = 1640,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask = 1641,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask_round = 1642,
  CODE_FOR_avx512f_fmaddsub_v8df_mask = 1643,
  CODE_FOR_avx512f_fmaddsub_v8df_mask_round = 1644,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask3 = 1645,
  CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round = 1646,
  CODE_FOR_avx512f_fmaddsub_v8df_mask3 = 1647,
  CODE_FOR_avx512f_fmaddsub_v8df_mask3_round = 1648,
#define CODE_FOR_fma_fmsubadd_v8sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v8sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4sf_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4sf_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v4df_maskz_1_round CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v2df_maskz_1 CODE_FOR_nothing
#define CODE_FOR_fma_fmsubadd_v2df_maskz_1_round CODE_FOR_nothing
  CODE_FOR_fma_fmsubadd_v16sf_maskz_1 = 1655,
  CODE_FOR_fma_fmsubadd_v16sf_maskz_1_round = 1656,
  CODE_FOR_fma_fmsubadd_v8df_maskz_1 = 1659,
  CODE_FOR_fma_fmsubadd_v8df_maskz_1_round = 1660,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask = 1661,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask_round = 1662,
  CODE_FOR_avx512f_fmsubadd_v8df_mask = 1663,
  CODE_FOR_avx512f_fmsubadd_v8df_mask_round = 1664,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask3 = 1665,
  CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round = 1666,
  CODE_FOR_avx512f_fmsubadd_v8df_mask3 = 1667,
  CODE_FOR_avx512f_fmsubadd_v8df_mask3_round = 1668,
  CODE_FOR_sse_cvtpi2ps = 1693,
  CODE_FOR_sse_cvtps2pi = 1694,
  CODE_FOR_sse_cvttps2pi = 1695,
  CODE_FOR_sse_cvtsi2ss = 1696,
  CODE_FOR_sse_cvtsi2ss_round = 1697,
  CODE_FOR_sse_cvtsi2ssq = 1698,
  CODE_FOR_sse_cvtsi2ssq_round = 1699,
  CODE_FOR_sse_cvtss2si = 1700,
  CODE_FOR_sse_cvtss2si_round = 1701,
  CODE_FOR_sse_cvtss2si_2 = 1702,
  CODE_FOR_sse_cvtss2siq = 1703,
  CODE_FOR_sse_cvtss2siq_round = 1704,
  CODE_FOR_sse_cvtss2siq_2 = 1705,
  CODE_FOR_sse_cvttss2si = 1706,
  CODE_FOR_sse_cvttss2si_round = 1707,
  CODE_FOR_sse_cvttss2siq = 1708,
  CODE_FOR_sse_cvttss2siq_round = 1709,
  CODE_FOR_cvtusi2ss32 = 1710,
  CODE_FOR_cvtusi2ss32_round = 1711,
  CODE_FOR_cvtusi2sd32 = 1712,
#define CODE_FOR_cvtusi2sd32_round CODE_FOR_nothing
  CODE_FOR_cvtusi2ss64 = 1713,
  CODE_FOR_cvtusi2ss64_round = 1714,
  CODE_FOR_cvtusi2sd64 = 1715,
  CODE_FOR_cvtusi2sd64_round = 1716,
  CODE_FOR_floatv16siv16sf2 = 1717,
  CODE_FOR_floatv16siv16sf2_round = 1718,
  CODE_FOR_floatv16siv16sf2_mask = 1719,
  CODE_FOR_floatv16siv16sf2_mask_round = 1720,
  CODE_FOR_floatv8siv8sf2 = 1721,
#define CODE_FOR_floatv8siv8sf2_round CODE_FOR_nothing
#define CODE_FOR_floatv8siv8sf2_mask CODE_FOR_nothing
#define CODE_FOR_floatv8siv8sf2_mask_round CODE_FOR_nothing
  CODE_FOR_floatv4siv4sf2 = 1722,
#define CODE_FOR_floatv4siv4sf2_round CODE_FOR_nothing
#define CODE_FOR_floatv4siv4sf2_mask CODE_FOR_nothing
#define CODE_FOR_floatv4siv4sf2_mask_round CODE_FOR_nothing
  CODE_FOR_ufloatv16siv16sf2 = 1723,
  CODE_FOR_ufloatv16siv16sf2_round = 1724,
  CODE_FOR_ufloatv16siv16sf2_mask = 1725,
  CODE_FOR_ufloatv16siv16sf2_mask_round = 1726,
  CODE_FOR_avx_fix_notruncv8sfv8si = 1727,
  CODE_FOR_sse2_fix_notruncv4sfv4si = 1728,
  CODE_FOR_avx512f_fix_notruncv16sfv16si_mask = 1731,
  CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round = 1732,
  CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask = 1735,
  CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round = 1736,
  CODE_FOR_fix_truncv16sfv16si2 = 1737,
  CODE_FOR_fix_truncv16sfv16si2_round = 1738,
  CODE_FOR_fix_truncv16sfv16si2_mask = 1739,
  CODE_FOR_fix_truncv16sfv16si2_mask_round = 1740,
  CODE_FOR_ufix_truncv16sfv16si2 = 1741,
  CODE_FOR_ufix_truncv16sfv16si2_round = 1742,
  CODE_FOR_ufix_truncv16sfv16si2_mask = 1743,
  CODE_FOR_ufix_truncv16sfv16si2_mask_round = 1744,
  CODE_FOR_fix_truncv8sfv8si2 = 1745,
  CODE_FOR_fix_truncv4sfv4si2 = 1746,
  CODE_FOR_sse2_cvtpi2pd = 1747,
  CODE_FOR_sse2_cvtpd2pi = 1748,
  CODE_FOR_sse2_cvttpd2pi = 1749,
  CODE_FOR_sse2_cvtsi2sd = 1750,
  CODE_FOR_sse2_cvtsi2sdq = 1751,
  CODE_FOR_sse2_cvtsi2sdq_round = 1752,
  CODE_FOR_avx512f_vcvtss2usi = 1753,
  CODE_FOR_avx512f_vcvtss2usi_round = 1754,
  CODE_FOR_avx512f_vcvtss2usiq = 1755,
  CODE_FOR_avx512f_vcvtss2usiq_round = 1756,
  CODE_FOR_avx512f_vcvttss2usi = 1757,
  CODE_FOR_avx512f_vcvttss2usi_round = 1758,
  CODE_FOR_avx512f_vcvttss2usiq = 1759,
  CODE_FOR_avx512f_vcvttss2usiq_round = 1760,
  CODE_FOR_avx512f_vcvtsd2usi = 1761,
  CODE_FOR_avx512f_vcvtsd2usi_round = 1762,
  CODE_FOR_avx512f_vcvtsd2usiq = 1763,
  CODE_FOR_avx512f_vcvtsd2usiq_round = 1764,
  CODE_FOR_avx512f_vcvttsd2usi = 1765,
  CODE_FOR_avx512f_vcvttsd2usi_round = 1766,
  CODE_FOR_avx512f_vcvttsd2usiq = 1767,
  CODE_FOR_avx512f_vcvttsd2usiq_round = 1768,
  CODE_FOR_sse2_cvtsd2si = 1769,
  CODE_FOR_sse2_cvtsd2si_round = 1770,
  CODE_FOR_sse2_cvtsd2si_2 = 1771,
  CODE_FOR_sse2_cvtsd2siq = 1772,
  CODE_FOR_sse2_cvtsd2siq_round = 1773,
  CODE_FOR_sse2_cvtsd2siq_2 = 1774,
  CODE_FOR_sse2_cvttsd2si = 1775,
  CODE_FOR_sse2_cvttsd2si_round = 1776,
  CODE_FOR_sse2_cvttsd2siq = 1777,
  CODE_FOR_sse2_cvttsd2siq_round = 1778,
  CODE_FOR_floatv8siv8df2 = 1779,
  CODE_FOR_floatv8siv8df2_mask = 1780,
  CODE_FOR_floatv4siv4df2 = 1781,
#define CODE_FOR_floatv4siv4df2_mask CODE_FOR_nothing
  CODE_FOR_ufloatv8siv8df = 1782,
  CODE_FOR_ufloatv8siv8df_mask = 1783,
  CODE_FOR_avx512f_cvtdq2pd512_2 = 1784,
  CODE_FOR_avx_cvtdq2pd256_2 = 1785,
  CODE_FOR_sse2_cvtdq2pd = 1786,
  CODE_FOR_avx512f_cvtpd2dq512_mask = 1789,
  CODE_FOR_avx512f_cvtpd2dq512_mask_round = 1790,
  CODE_FOR_avx_cvtpd2dq256 = 1791,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si = 1794,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si_round = 1795,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask = 1796,
  CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round = 1797,
  CODE_FOR_fix_truncv8dfv8si2 = 1798,
  CODE_FOR_fix_truncv8dfv8si2_round = 1799,
  CODE_FOR_fix_truncv8dfv8si2_mask = 1800,
  CODE_FOR_fix_truncv8dfv8si2_mask_round = 1801,
  CODE_FOR_ufix_truncv8dfv8si2 = 1802,
  CODE_FOR_ufix_truncv8dfv8si2_round = 1803,
  CODE_FOR_ufix_truncv8dfv8si2_mask = 1804,
  CODE_FOR_ufix_truncv8dfv8si2_mask_round = 1805,
  CODE_FOR_fix_truncv4dfv4si2 = 1806,
  CODE_FOR_sse2_cvtsd2ss = 1809,
  CODE_FOR_sse2_cvtsd2ss_round = 1810,
  CODE_FOR_sse2_cvtss2sd = 1811,
  CODE_FOR_sse2_cvtss2sd_round = 1812,
  CODE_FOR_avx512f_cvtpd2ps512_mask = 1815,
  CODE_FOR_avx512f_cvtpd2ps512_mask_round = 1816,
  CODE_FOR_avx_cvtpd2ps256 = 1817,
  CODE_FOR_avx512f_cvtps2pd512 = 1819,
  CODE_FOR_avx512f_cvtps2pd512_round = 1820,
  CODE_FOR_avx512f_cvtps2pd512_mask = 1821,
  CODE_FOR_avx512f_cvtps2pd512_mask_round = 1822,
  CODE_FOR_avx_cvtps2pd256 = 1823,
#define CODE_FOR_avx_cvtps2pd256_round CODE_FOR_nothing
#define CODE_FOR_avx_cvtps2pd256_mask CODE_FOR_nothing
#define CODE_FOR_avx_cvtps2pd256_mask_round CODE_FOR_nothing
  CODE_FOR_vec_unpacks_lo_v16sf = 1825,
  CODE_FOR_sse2_cvtps2pd = 1826,
  CODE_FOR_sse_movhlps = 1827,
  CODE_FOR_sse_movlhps = 1828,
  CODE_FOR_avx512f_unpckhps512_mask = 1830,
  CODE_FOR_avx_unpckhps256 = 1831,
  CODE_FOR_vec_interleave_highv4sf = 1832,
  CODE_FOR_avx512f_unpcklps512_mask = 1834,
  CODE_FOR_avx_unpcklps256 = 1835,
  CODE_FOR_vec_interleave_lowv4sf = 1836,
  CODE_FOR_avx_movshdup256 = 1837,
  CODE_FOR_sse3_movshdup = 1838,
  CODE_FOR_avx512f_movshdup512_mask = 1840,
  CODE_FOR_avx_movsldup256 = 1841,
  CODE_FOR_sse3_movsldup = 1842,
  CODE_FOR_avx512f_movsldup512_mask = 1844,
  CODE_FOR_avx_shufps256_1 = 1845,
  CODE_FOR_sse_shufps_v4si = 1846,
  CODE_FOR_sse_shufps_v4sf = 1847,
  CODE_FOR_sse_storehps = 1848,
  CODE_FOR_sse_loadhps = 1849,
  CODE_FOR_sse_storelps = 1850,
  CODE_FOR_sse_loadlps = 1851,
  CODE_FOR_sse_movss = 1852,
  CODE_FOR_avx2_vec_dupv8sf = 1853,
  CODE_FOR_avx2_vec_dupv4sf = 1854,
  CODE_FOR_avx2_vec_dupv8sf_1 = 1855,
  CODE_FOR_vec_dupv4sf = 1856,
  CODE_FOR_vec_setv4si_0 = 1860,
  CODE_FOR_vec_setv4sf_0 = 1861,
  CODE_FOR_sse4_1_insertps = 1863,
  CODE_FOR_avx512f_vextractf32x4_1_maskm = 1867,
  CODE_FOR_avx512f_vextracti32x4_1_maskm = 1868,
  CODE_FOR_avx512f_vextractf32x4_1_mask = 1870,
  CODE_FOR_avx512f_vextracti32x4_1_mask = 1872,
  CODE_FOR_vec_extract_lo_v8df_maskm = 1873,
  CODE_FOR_vec_extract_lo_v8di_maskm = 1874,
  CODE_FOR_vec_extract_lo_v8df = 1875,
  CODE_FOR_vec_extract_lo_v8df_mask = 1876,
  CODE_FOR_vec_extract_lo_v8di = 1877,
  CODE_FOR_vec_extract_lo_v8di_mask = 1878,
  CODE_FOR_vec_extract_hi_v8df_maskm = 1879,
  CODE_FOR_vec_extract_hi_v8di_maskm = 1880,
  CODE_FOR_vec_extract_hi_v8df = 1881,
  CODE_FOR_vec_extract_hi_v8df_mask = 1882,
  CODE_FOR_vec_extract_hi_v8di = 1883,
  CODE_FOR_vec_extract_hi_v8di_mask = 1884,
  CODE_FOR_vec_extract_lo_v16sf = 1885,
  CODE_FOR_vec_extract_lo_v16si = 1886,
  CODE_FOR_vec_extract_hi_v16sf = 1887,
  CODE_FOR_vec_extract_hi_v16si = 1888,
  CODE_FOR_vec_extract_lo_v4di = 1889,
  CODE_FOR_vec_extract_lo_v4df = 1890,
  CODE_FOR_vec_extract_hi_v4di = 1891,
  CODE_FOR_vec_extract_hi_v4df = 1892,
  CODE_FOR_vec_extract_lo_v8si = 1893,
  CODE_FOR_vec_extract_lo_v8sf = 1894,
  CODE_FOR_vec_extract_hi_v8si = 1895,
  CODE_FOR_vec_extract_hi_v8sf = 1896,
  CODE_FOR_vec_extract_lo_v32hi = 1897,
  CODE_FOR_vec_extract_hi_v32hi = 1898,
  CODE_FOR_vec_extract_lo_v16hi = 1899,
  CODE_FOR_vec_extract_hi_v16hi = 1900,
  CODE_FOR_vec_extract_lo_v64qi = 1901,
  CODE_FOR_vec_extract_hi_v64qi = 1902,
  CODE_FOR_vec_extract_lo_v32qi = 1903,
  CODE_FOR_vec_extract_hi_v32qi = 1904,
  CODE_FOR_avx512f_unpckhpd512_mask = 1906,
  CODE_FOR_avx_unpckhpd256 = 1907,
  CODE_FOR_avx512f_vmscalefv4sf = 1913,
  CODE_FOR_avx512f_vmscalefv4sf_round = 1914,
  CODE_FOR_avx512f_vmscalefv2df = 1915,
  CODE_FOR_avx512f_vmscalefv2df_round = 1916,
  CODE_FOR_avx512f_scalefv16sf = 1917,
  CODE_FOR_avx512f_scalefv16sf_round = 1918,
  CODE_FOR_avx512f_scalefv16sf_mask = 1919,
  CODE_FOR_avx512f_scalefv16sf_mask_round = 1920,
  CODE_FOR_avx512f_scalefv8df = 1921,
  CODE_FOR_avx512f_scalefv8df_round = 1922,
  CODE_FOR_avx512f_scalefv8df_mask = 1923,
  CODE_FOR_avx512f_scalefv8df_mask_round = 1924,
  CODE_FOR_avx512f_vternlogv16si = 1925,
  CODE_FOR_avx512f_vternlogv16si_maskz_1 = 1926,
  CODE_FOR_avx512f_vternlogv8di = 1927,
  CODE_FOR_avx512f_vternlogv8di_maskz_1 = 1928,
  CODE_FOR_avx512f_vternlogv16si_mask = 1929,
  CODE_FOR_avx512f_vternlogv8di_mask = 1930,
  CODE_FOR_avx512f_getexpv16sf = 1931,
  CODE_FOR_avx512f_getexpv16sf_round = 1932,
  CODE_FOR_avx512f_getexpv16sf_mask = 1933,
  CODE_FOR_avx512f_getexpv16sf_mask_round = 1934,
  CODE_FOR_avx512f_getexpv8df = 1935,
  CODE_FOR_avx512f_getexpv8df_round = 1936,
  CODE_FOR_avx512f_getexpv8df_mask = 1937,
  CODE_FOR_avx512f_getexpv8df_mask_round = 1938,
  CODE_FOR_avx512f_sgetexpv4sf = 1939,
  CODE_FOR_avx512f_sgetexpv4sf_round = 1940,
  CODE_FOR_avx512f_sgetexpv2df = 1941,
  CODE_FOR_avx512f_sgetexpv2df_round = 1942,
  CODE_FOR_avx512f_alignv16si_mask = 1944,
  CODE_FOR_avx512f_alignv8di_mask = 1946,
  CODE_FOR_avx512f_fixupimmv16sf = 1947,
  CODE_FOR_avx512f_fixupimmv16sf_round = 1948,
  CODE_FOR_avx512f_fixupimmv16sf_maskz_1 = 1949,
  CODE_FOR_avx512f_fixupimmv16sf_maskz_1_round = 1950,
  CODE_FOR_avx512f_fixupimmv8df = 1951,
  CODE_FOR_avx512f_fixupimmv8df_round = 1952,
  CODE_FOR_avx512f_fixupimmv8df_maskz_1 = 1953,
  CODE_FOR_avx512f_fixupimmv8df_maskz_1_round = 1954,
  CODE_FOR_avx512f_fixupimmv16sf_mask = 1955,
  CODE_FOR_avx512f_fixupimmv16sf_mask_round = 1956,
  CODE_FOR_avx512f_fixupimmv8df_mask = 1957,
  CODE_FOR_avx512f_fixupimmv8df_mask_round = 1958,
  CODE_FOR_avx512f_sfixupimmv4sf = 1959,
  CODE_FOR_avx512f_sfixupimmv4sf_round = 1960,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz_1 = 1961,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz_1_round = 1962,
  CODE_FOR_avx512f_sfixupimmv2df = 1963,
  CODE_FOR_avx512f_sfixupimmv2df_round = 1964,
  CODE_FOR_avx512f_sfixupimmv2df_maskz_1 = 1965,
  CODE_FOR_avx512f_sfixupimmv2df_maskz_1_round = 1966,
  CODE_FOR_avx512f_sfixupimmv4sf_mask = 1967,
  CODE_FOR_avx512f_sfixupimmv4sf_mask_round = 1968,
  CODE_FOR_avx512f_sfixupimmv2df_mask = 1969,
  CODE_FOR_avx512f_sfixupimmv2df_mask_round = 1970,
  CODE_FOR_avx512f_rndscalev16sf = 1971,
  CODE_FOR_avx512f_rndscalev16sf_round = 1972,
  CODE_FOR_avx512f_rndscalev16sf_mask = 1973,
  CODE_FOR_avx512f_rndscalev16sf_mask_round = 1974,
  CODE_FOR_avx512f_rndscalev8df = 1975,
  CODE_FOR_avx512f_rndscalev8df_round = 1976,
  CODE_FOR_avx512f_rndscalev8df_mask = 1977,
  CODE_FOR_avx512f_rndscalev8df_mask_round = 1978,
  CODE_FOR_avx512f_rndscalev4sf = 1979,
  CODE_FOR_avx512f_rndscalev4sf_round = 1980,
  CODE_FOR_avx512f_rndscalev2df = 1981,
  CODE_FOR_avx512f_rndscalev2df_round = 1982,
  CODE_FOR_avx512f_shufps512_1 = 1983,
  CODE_FOR_avx512f_shufps512_1_mask = 1984,
  CODE_FOR_avx512f_shufpd512_1 = 1985,
  CODE_FOR_avx512f_shufpd512_1_mask = 1986,
  CODE_FOR_avx_shufpd256_1 = 1987,
  CODE_FOR_avx2_interleave_highv4di = 1988,
  CODE_FOR_avx512f_interleave_highv8di_mask = 1990,
  CODE_FOR_vec_interleave_highv2di = 1991,
  CODE_FOR_avx2_interleave_lowv4di = 1992,
  CODE_FOR_avx512f_interleave_lowv8di_mask = 1994,
  CODE_FOR_vec_interleave_lowv2di = 1995,
  CODE_FOR_sse2_shufpd_v2di = 1996,
  CODE_FOR_sse2_shufpd_v2df = 1997,
  CODE_FOR_sse2_storehpd = 1998,
  CODE_FOR_sse2_storelpd = 2000,
  CODE_FOR_sse2_loadhpd = 2002,
  CODE_FOR_sse2_loadlpd = 2003,
  CODE_FOR_sse2_movsd = 2004,
  CODE_FOR_vec_dupv2df = 2005,
  CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask = 2019,
  CODE_FOR_avx512f_truncatev16siv16qi2_mask = 2020,
  CODE_FOR_avx512f_us_truncatev16siv16qi2_mask = 2021,
  CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask = 2022,
  CODE_FOR_avx512f_truncatev16siv16hi2_mask = 2023,
  CODE_FOR_avx512f_us_truncatev16siv16hi2_mask = 2024,
  CODE_FOR_avx512f_ss_truncatev8div8si2_mask = 2025,
  CODE_FOR_avx512f_truncatev8div8si2_mask = 2026,
  CODE_FOR_avx512f_us_truncatev8div8si2_mask = 2027,
  CODE_FOR_avx512f_ss_truncatev8div8hi2_mask = 2028,
  CODE_FOR_avx512f_truncatev8div8hi2_mask = 2029,
  CODE_FOR_avx512f_us_truncatev8div8hi2_mask = 2030,
  CODE_FOR_avx512f_ss_truncatev8div16qi2_mask = 2037,
  CODE_FOR_avx512f_truncatev8div16qi2_mask = 2038,
  CODE_FOR_avx512f_us_truncatev8div16qi2_mask = 2039,
  CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store = 2040,
  CODE_FOR_avx512f_truncatev8div16qi2_mask_store = 2041,
  CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store = 2042,
  CODE_FOR_ashrv16hi3 = 2119,
  CODE_FOR_ashrv8hi3 = 2120,
  CODE_FOR_ashrv8si3 = 2121,
  CODE_FOR_ashrv4si3 = 2122,
  CODE_FOR_ashrv16si3 = 2123,
  CODE_FOR_ashrv16si3_mask = 2124,
  CODE_FOR_ashrv8di3 = 2125,
  CODE_FOR_ashrv8di3_mask = 2126,
  CODE_FOR_ashlv16hi3 = 2127,
  CODE_FOR_lshrv16hi3 = 2128,
  CODE_FOR_ashlv8hi3 = 2129,
  CODE_FOR_lshrv8hi3 = 2130,
  CODE_FOR_ashlv8si3 = 2131,
  CODE_FOR_lshrv8si3 = 2132,
  CODE_FOR_ashlv4si3 = 2133,
  CODE_FOR_lshrv4si3 = 2134,
  CODE_FOR_ashlv4di3 = 2135,
  CODE_FOR_lshrv4di3 = 2136,
  CODE_FOR_ashlv2di3 = 2137,
  CODE_FOR_lshrv2di3 = 2138,
  CODE_FOR_ashlv16si3 = 2139,
  CODE_FOR_ashlv16si3_mask = 2140,
  CODE_FOR_lshrv16si3 = 2141,
  CODE_FOR_lshrv16si3_mask = 2142,
  CODE_FOR_ashlv8di3 = 2143,
  CODE_FOR_ashlv8di3_mask = 2144,
  CODE_FOR_lshrv8di3 = 2145,
  CODE_FOR_lshrv8di3_mask = 2146,
  CODE_FOR_avx2_ashlv2ti3 = 2147,
  CODE_FOR_sse2_ashlv1ti3 = 2148,
  CODE_FOR_avx2_lshrv2ti3 = 2149,
  CODE_FOR_sse2_lshrv1ti3 = 2150,
  CODE_FOR_avx512f_rolvv16si = 2151,
  CODE_FOR_avx512f_rolvv16si_mask = 2152,
  CODE_FOR_avx512f_rorvv16si = 2153,
  CODE_FOR_avx512f_rorvv16si_mask = 2154,
  CODE_FOR_avx512f_rolvv8di = 2155,
  CODE_FOR_avx512f_rolvv8di_mask = 2156,
  CODE_FOR_avx512f_rorvv8di = 2157,
  CODE_FOR_avx512f_rorvv8di_mask = 2158,
  CODE_FOR_avx512f_rolv16si = 2159,
  CODE_FOR_avx512f_rolv16si_mask = 2160,
  CODE_FOR_avx512f_rorv16si = 2161,
  CODE_FOR_avx512f_rorv16si_mask = 2162,
  CODE_FOR_avx512f_rolv8di = 2163,
  CODE_FOR_avx512f_rolv8di_mask = 2164,
  CODE_FOR_avx512f_rorv8di = 2165,
  CODE_FOR_avx512f_rorv8di_mask = 2166,
  CODE_FOR_avx512f_eqv16si3_1 = 2251,
  CODE_FOR_avx512f_eqv16si3_mask_1 = 2252,
  CODE_FOR_avx512f_eqv8di3_1 = 2253,
  CODE_FOR_avx512f_eqv8di3_mask_1 = 2254,
  CODE_FOR_sse4_2_gtv2di3 = 2259,
  CODE_FOR_avx2_gtv32qi3 = 2260,
  CODE_FOR_avx2_gtv16hi3 = 2261,
  CODE_FOR_avx2_gtv8si3 = 2262,
  CODE_FOR_avx2_gtv4di3 = 2263,
  CODE_FOR_avx512f_gtv16si3 = 2264,
  CODE_FOR_avx512f_gtv16si3_mask = 2265,
  CODE_FOR_avx512f_gtv8di3 = 2266,
  CODE_FOR_avx512f_gtv8di3_mask = 2267,
  CODE_FOR_sse2_gtv16qi3 = 2268,
  CODE_FOR_sse2_gtv8hi3 = 2269,
  CODE_FOR_sse2_gtv4si3 = 2270,
  CODE_FOR_andv16si3_mask = 2284,
  CODE_FOR_iorv16si3_mask = 2286,
  CODE_FOR_xorv16si3_mask = 2288,
  CODE_FOR_andv8di3_mask = 2290,
  CODE_FOR_iorv8di3_mask = 2292,
  CODE_FOR_xorv8di3_mask = 2294,
#define CODE_FOR_andv16qi3_mask CODE_FOR_nothing
#define CODE_FOR_iorv16qi3_mask CODE_FOR_nothing
#define CODE_FOR_xorv16qi3_mask CODE_FOR_nothing
#define CODE_FOR_andv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_iorv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_xorv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_andv8hi3_mask CODE_FOR_nothing
#define CODE_FOR_iorv8hi3_mask CODE_FOR_nothing
#define CODE_FOR_xorv8hi3_mask CODE_FOR_nothing
#define CODE_FOR_andv8si3_mask CODE_FOR_nothing
#define CODE_FOR_iorv8si3_mask CODE_FOR_nothing
#define CODE_FOR_xorv8si3_mask CODE_FOR_nothing
#define CODE_FOR_andv4si3_mask CODE_FOR_nothing
#define CODE_FOR_iorv4si3_mask CODE_FOR_nothing
#define CODE_FOR_xorv4si3_mask CODE_FOR_nothing
#define CODE_FOR_andv4di3_mask CODE_FOR_nothing
#define CODE_FOR_iorv4di3_mask CODE_FOR_nothing
#define CODE_FOR_xorv4di3_mask CODE_FOR_nothing
#define CODE_FOR_andv2di3_mask CODE_FOR_nothing
#define CODE_FOR_iorv2di3_mask CODE_FOR_nothing
#define CODE_FOR_xorv2di3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_testmv16si3 = 2319,
  CODE_FOR_avx512f_testmv16si3_mask = 2320,
  CODE_FOR_avx512f_testmv8di3 = 2321,
  CODE_FOR_avx512f_testmv8di3_mask = 2322,
  CODE_FOR_avx512f_testnmv16si3 = 2323,
  CODE_FOR_avx512f_testnmv16si3_mask = 2324,
  CODE_FOR_avx512f_testnmv8di3 = 2325,
  CODE_FOR_avx512f_testnmv8di3_mask = 2326,
  CODE_FOR_avx2_packsswb = 2327,
  CODE_FOR_sse2_packsswb = 2328,
  CODE_FOR_avx2_packssdw = 2329,
  CODE_FOR_sse2_packssdw = 2330,
  CODE_FOR_avx2_packuswb = 2331,
  CODE_FOR_sse2_packuswb = 2332,
  CODE_FOR_avx2_interleave_highv32qi = 2333,
  CODE_FOR_vec_interleave_highv16qi = 2334,
  CODE_FOR_avx2_interleave_lowv32qi = 2335,
  CODE_FOR_vec_interleave_lowv16qi = 2336,
  CODE_FOR_avx2_interleave_highv16hi = 2337,
  CODE_FOR_vec_interleave_highv8hi = 2338,
  CODE_FOR_avx2_interleave_lowv16hi = 2339,
  CODE_FOR_vec_interleave_lowv8hi = 2340,
  CODE_FOR_avx2_interleave_highv8si = 2341,
  CODE_FOR_avx512f_interleave_highv16si_mask = 2343,
  CODE_FOR_vec_interleave_highv4si = 2344,
  CODE_FOR_avx2_interleave_lowv8si = 2345,
  CODE_FOR_avx512f_interleave_lowv16si_mask = 2347,
  CODE_FOR_vec_interleave_lowv4si = 2348,
  CODE_FOR_sse4_1_pinsrb = 2349,
  CODE_FOR_sse2_pinsrw = 2350,
  CODE_FOR_sse4_1_pinsrd = 2351,
  CODE_FOR_sse4_1_pinsrq = 2352,
  CODE_FOR_avx512f_vinsertf32x4_1_mask = 2354,
  CODE_FOR_avx512f_vinserti32x4_1_mask = 2356,
  CODE_FOR_vec_set_lo_v8df = 2357,
  CODE_FOR_vec_set_lo_v8df_mask = 2358,
  CODE_FOR_vec_set_lo_v8di = 2359,
  CODE_FOR_vec_set_lo_v8di_mask = 2360,
  CODE_FOR_vec_set_hi_v8df = 2361,
  CODE_FOR_vec_set_hi_v8df_mask = 2362,
  CODE_FOR_vec_set_hi_v8di = 2363,
  CODE_FOR_vec_set_hi_v8di_mask = 2364,
  CODE_FOR_avx512f_shuf_f64x2_1 = 2365,
  CODE_FOR_avx512f_shuf_f64x2_1_mask = 2366,
  CODE_FOR_avx512f_shuf_i64x2_1 = 2367,
  CODE_FOR_avx512f_shuf_i64x2_1_mask = 2368,
  CODE_FOR_avx512f_shuf_f32x4_1 = 2369,
  CODE_FOR_avx512f_shuf_f32x4_1_mask = 2370,
  CODE_FOR_avx512f_shuf_i32x4_1 = 2371,
  CODE_FOR_avx512f_shuf_i32x4_1_mask = 2372,
  CODE_FOR_avx512f_pshufd_1 = 2373,
  CODE_FOR_avx512f_pshufd_1_mask = 2374,
  CODE_FOR_avx2_pshufd_1 = 2375,
  CODE_FOR_sse2_pshufd_1 = 2376,
  CODE_FOR_avx2_pshuflw_1 = 2377,
  CODE_FOR_sse2_pshuflw_1 = 2378,
  CODE_FOR_avx2_pshufhw_1 = 2379,
  CODE_FOR_sse2_pshufhw_1 = 2380,
  CODE_FOR_sse2_loadld = 2381,
  CODE_FOR_vec_concatv2di = 2405,
  CODE_FOR_avx2_psadbw = 2410,
  CODE_FOR_sse2_psadbw = 2411,
  CODE_FOR_avx_movmskps256 = 2412,
  CODE_FOR_sse_movmskps = 2413,
  CODE_FOR_avx_movmskpd256 = 2414,
  CODE_FOR_sse2_movmskpd = 2415,
  CODE_FOR_avx2_pmovmskb = 2416,
  CODE_FOR_sse2_pmovmskb = 2417,
  CODE_FOR_sse_ldmxcsr = 2420,
  CODE_FOR_sse_stmxcsr = 2421,
  CODE_FOR_sse2_clflush = 2422,
  CODE_FOR_sse3_mwait = 2423,
  CODE_FOR_sse3_monitor_si = 2424,
  CODE_FOR_sse3_monitor_di = 2425,
  CODE_FOR_avx2_phaddwv16hi3 = 2426,
  CODE_FOR_avx2_phaddswv16hi3 = 2427,
  CODE_FOR_avx2_phsubwv16hi3 = 2428,
  CODE_FOR_avx2_phsubswv16hi3 = 2429,
  CODE_FOR_ssse3_phaddwv8hi3 = 2430,
  CODE_FOR_ssse3_phaddswv8hi3 = 2431,
  CODE_FOR_ssse3_phsubwv8hi3 = 2432,
  CODE_FOR_ssse3_phsubswv8hi3 = 2433,
  CODE_FOR_ssse3_phaddwv4hi3 = 2434,
  CODE_FOR_ssse3_phaddswv4hi3 = 2435,
  CODE_FOR_ssse3_phsubwv4hi3 = 2436,
  CODE_FOR_ssse3_phsubswv4hi3 = 2437,
  CODE_FOR_avx2_phadddv8si3 = 2438,
  CODE_FOR_avx2_phsubdv8si3 = 2439,
  CODE_FOR_ssse3_phadddv4si3 = 2440,
  CODE_FOR_ssse3_phsubdv4si3 = 2441,
  CODE_FOR_ssse3_phadddv2si3 = 2442,
  CODE_FOR_ssse3_phsubdv2si3 = 2443,
  CODE_FOR_avx2_pmaddubsw256 = 2444,
  CODE_FOR_ssse3_pmaddubsw128 = 2445,
  CODE_FOR_ssse3_pmaddubsw = 2446,
  CODE_FOR_avx2_pshufbv32qi3 = 2450,
  CODE_FOR_ssse3_pshufbv16qi3 = 2451,
  CODE_FOR_ssse3_pshufbv8qi3 = 2452,
  CODE_FOR_avx2_psignv32qi3 = 2453,
  CODE_FOR_ssse3_psignv16qi3 = 2454,
  CODE_FOR_avx2_psignv16hi3 = 2455,
  CODE_FOR_ssse3_psignv8hi3 = 2456,
  CODE_FOR_avx2_psignv8si3 = 2457,
  CODE_FOR_ssse3_psignv4si3 = 2458,
  CODE_FOR_ssse3_psignv8qi3 = 2459,
  CODE_FOR_ssse3_psignv4hi3 = 2460,
  CODE_FOR_ssse3_psignv2si3 = 2461,
  CODE_FOR_avx2_palignrv2ti = 2462,
  CODE_FOR_ssse3_palignrti = 2463,
  CODE_FOR_ssse3_palignrdi = 2464,
#define CODE_FOR_absv16qi2_mask CODE_FOR_nothing
#define CODE_FOR_absv16hi2_mask CODE_FOR_nothing
#define CODE_FOR_absv8hi2_mask CODE_FOR_nothing
  CODE_FOR_absv16si2_mask = 2470,
#define CODE_FOR_absv8si2_mask CODE_FOR_nothing
#define CODE_FOR_absv4si2_mask CODE_FOR_nothing
  CODE_FOR_absv8di2_mask = 2474,
  CODE_FOR_absv8qi2 = 2475,
  CODE_FOR_absv4hi2 = 2476,
  CODE_FOR_absv2si2 = 2477,
  CODE_FOR_sse4a_movntsf = 2478,
  CODE_FOR_sse4a_movntdf = 2479,
  CODE_FOR_sse4a_vmmovntv4sf = 2480,
  CODE_FOR_sse4a_vmmovntv2df = 2481,
  CODE_FOR_sse4a_extrqi = 2482,
  CODE_FOR_sse4a_extrq = 2483,
  CODE_FOR_sse4a_insertqi = 2484,
  CODE_FOR_sse4a_insertq = 2485,
  CODE_FOR_avx_blendps256 = 2486,
  CODE_FOR_sse4_1_blendps = 2487,
  CODE_FOR_avx_blendpd256 = 2488,
  CODE_FOR_sse4_1_blendpd = 2489,
  CODE_FOR_avx_blendvps256 = 2490,
  CODE_FOR_sse4_1_blendvps = 2491,
  CODE_FOR_avx_blendvpd256 = 2492,
  CODE_FOR_sse4_1_blendvpd = 2493,
  CODE_FOR_avx_dpps256 = 2494,
  CODE_FOR_sse4_1_dpps = 2495,
  CODE_FOR_avx_dppd256 = 2496,
  CODE_FOR_sse4_1_dppd = 2497,
  CODE_FOR_avx512f_movntdqa = 2498,
  CODE_FOR_avx2_movntdqa = 2499,
  CODE_FOR_sse4_1_movntdqa = 2500,
  CODE_FOR_avx2_mpsadbw = 2501,
  CODE_FOR_sse4_1_mpsadbw = 2502,
  CODE_FOR_avx2_packusdw = 2503,
  CODE_FOR_sse4_1_packusdw = 2504,
  CODE_FOR_avx2_pblendvb = 2505,
  CODE_FOR_sse4_1_pblendvb = 2506,
  CODE_FOR_sse4_1_pblendw = 2507,
  CODE_FOR_avx2_pblenddv8si = 2509,
  CODE_FOR_avx2_pblenddv4si = 2510,
  CODE_FOR_sse4_1_phminposuw = 2511,
  CODE_FOR_avx2_sign_extendv16qiv16hi2 = 2512,
  CODE_FOR_avx2_zero_extendv16qiv16hi2 = 2513,
  CODE_FOR_sse4_1_sign_extendv8qiv8hi2 = 2514,
  CODE_FOR_sse4_1_zero_extendv8qiv8hi2 = 2515,
  CODE_FOR_avx512f_sign_extendv16qiv16si2_mask = 2517,
  CODE_FOR_avx512f_zero_extendv16qiv16si2_mask = 2519,
  CODE_FOR_avx2_sign_extendv8qiv8si2 = 2520,
  CODE_FOR_avx2_zero_extendv8qiv8si2 = 2521,
  CODE_FOR_sse4_1_sign_extendv4qiv4si2 = 2522,
  CODE_FOR_sse4_1_zero_extendv4qiv4si2 = 2523,
  CODE_FOR_avx512f_sign_extendv16hiv16si2 = 2524,
  CODE_FOR_avx512f_sign_extendv16hiv16si2_mask = 2525,
  CODE_FOR_avx512f_zero_extendv16hiv16si2 = 2526,
  CODE_FOR_avx512f_zero_extendv16hiv16si2_mask = 2527,
  CODE_FOR_avx2_sign_extendv8hiv8si2 = 2528,
  CODE_FOR_avx2_zero_extendv8hiv8si2 = 2529,
  CODE_FOR_sse4_1_sign_extendv4hiv4si2 = 2530,
  CODE_FOR_sse4_1_zero_extendv4hiv4si2 = 2531,
  CODE_FOR_avx512f_sign_extendv8qiv8di2 = 2532,
  CODE_FOR_avx512f_sign_extendv8qiv8di2_mask = 2533,
  CODE_FOR_avx512f_zero_extendv8qiv8di2 = 2534,
  CODE_FOR_avx512f_zero_extendv8qiv8di2_mask = 2535,
  CODE_FOR_avx2_sign_extendv4qiv4di2 = 2536,
  CODE_FOR_avx2_zero_extendv4qiv4di2 = 2537,
  CODE_FOR_sse4_1_sign_extendv2qiv2di2 = 2538,
  CODE_FOR_sse4_1_zero_extendv2qiv2di2 = 2539,
  CODE_FOR_avx512f_sign_extendv8hiv8di2 = 2540,
  CODE_FOR_avx512f_sign_extendv8hiv8di2_mask = 2541,
  CODE_FOR_avx512f_zero_extendv8hiv8di2 = 2542,
  CODE_FOR_avx512f_zero_extendv8hiv8di2_mask = 2543,
  CODE_FOR_avx2_sign_extendv4hiv4di2 = 2544,
  CODE_FOR_avx2_zero_extendv4hiv4di2 = 2545,
  CODE_FOR_sse4_1_sign_extendv2hiv2di2 = 2546,
  CODE_FOR_sse4_1_zero_extendv2hiv2di2 = 2547,
  CODE_FOR_avx512f_sign_extendv8siv8di2 = 2548,
  CODE_FOR_avx512f_sign_extendv8siv8di2_mask = 2549,
  CODE_FOR_avx512f_zero_extendv8siv8di2 = 2550,
  CODE_FOR_avx512f_zero_extendv8siv8di2_mask = 2551,
  CODE_FOR_avx2_sign_extendv4siv4di2 = 2552,
  CODE_FOR_avx2_zero_extendv4siv4di2 = 2553,
  CODE_FOR_sse4_1_sign_extendv2siv2di2 = 2554,
  CODE_FOR_sse4_1_zero_extendv2siv2di2 = 2555,
  CODE_FOR_avx_vtestps256 = 2556,
  CODE_FOR_avx_vtestps = 2557,
  CODE_FOR_avx_vtestpd256 = 2558,
  CODE_FOR_avx_vtestpd = 2559,
  CODE_FOR_avx_ptest256 = 2560,
  CODE_FOR_sse4_1_ptest = 2561,
  CODE_FOR_avx_roundps256 = 2562,
  CODE_FOR_sse4_1_roundps = 2563,
  CODE_FOR_avx_roundpd256 = 2564,
  CODE_FOR_sse4_1_roundpd = 2565,
  CODE_FOR_sse4_1_roundss = 2566,
  CODE_FOR_sse4_1_roundsd = 2567,
  CODE_FOR_sse4_2_pcmpestr = 2568,
  CODE_FOR_sse4_2_pcmpestri = 2570,
  CODE_FOR_sse4_2_pcmpestrm = 2571,
  CODE_FOR_sse4_2_pcmpestr_cconly = 2572,
  CODE_FOR_sse4_2_pcmpistr = 2573,
  CODE_FOR_sse4_2_pcmpistri = 2575,
  CODE_FOR_sse4_2_pcmpistrm = 2576,
  CODE_FOR_sse4_2_pcmpistr_cconly = 2577,
  CODE_FOR_avx512er_exp2v16sf = 2610,
  CODE_FOR_avx512er_exp2v16sf_round = 2611,
  CODE_FOR_avx512er_exp2v16sf_mask = 2612,
  CODE_FOR_avx512er_exp2v16sf_mask_round = 2613,
  CODE_FOR_avx512er_exp2v8df = 2614,
  CODE_FOR_avx512er_exp2v8df_round = 2615,
  CODE_FOR_avx512er_exp2v8df_mask = 2616,
  CODE_FOR_avx512er_exp2v8df_mask_round = 2617,
  CODE_FOR_avx512er_rcp28v16sf_mask = 2620,
  CODE_FOR_avx512er_rcp28v16sf_mask_round = 2621,
  CODE_FOR_avx512er_rcp28v8df_mask = 2624,
  CODE_FOR_avx512er_rcp28v8df_mask_round = 2625,
  CODE_FOR_avx512er_vmrcp28v4sf = 2626,
  CODE_FOR_avx512er_vmrcp28v4sf_round = 2627,
  CODE_FOR_avx512er_vmrcp28v2df = 2628,
  CODE_FOR_avx512er_vmrcp28v2df_round = 2629,
  CODE_FOR_avx512er_rsqrt28v16sf_mask = 2632,
  CODE_FOR_avx512er_rsqrt28v16sf_mask_round = 2633,
  CODE_FOR_avx512er_rsqrt28v8df_mask = 2636,
  CODE_FOR_avx512er_rsqrt28v8df_mask_round = 2637,
  CODE_FOR_avx512er_vmrsqrt28v4sf = 2638,
  CODE_FOR_avx512er_vmrsqrt28v4sf_round = 2639,
  CODE_FOR_avx512er_vmrsqrt28v2df = 2640,
  CODE_FOR_avx512er_vmrsqrt28v2df_round = 2641,
  CODE_FOR_xop_pmacsww = 2642,
  CODE_FOR_xop_pmacssww = 2643,
  CODE_FOR_xop_pmacsdd = 2644,
  CODE_FOR_xop_pmacssdd = 2645,
  CODE_FOR_xop_pmacsdql = 2646,
  CODE_FOR_xop_pmacssdql = 2647,
  CODE_FOR_xop_pmacsdqh = 2648,
  CODE_FOR_xop_pmacssdqh = 2649,
  CODE_FOR_xop_pmacswd = 2650,
  CODE_FOR_xop_pmacsswd = 2651,
  CODE_FOR_xop_pmadcswd = 2652,
  CODE_FOR_xop_pmadcsswd = 2653,
  CODE_FOR_xop_pcmov_v32qi256 = 2654,
  CODE_FOR_xop_pcmov_v16qi = 2655,
  CODE_FOR_xop_pcmov_v16hi256 = 2656,
  CODE_FOR_xop_pcmov_v8hi = 2657,
  CODE_FOR_xop_pcmov_v16si512 = 2658,
  CODE_FOR_xop_pcmov_v8si256 = 2659,
  CODE_FOR_xop_pcmov_v4si = 2660,
  CODE_FOR_xop_pcmov_v8di512 = 2661,
  CODE_FOR_xop_pcmov_v4di256 = 2662,
  CODE_FOR_xop_pcmov_v2di = 2663,
  CODE_FOR_xop_pcmov_v16sf512 = 2664,
  CODE_FOR_xop_pcmov_v8sf256 = 2665,
  CODE_FOR_xop_pcmov_v4sf = 2666,
  CODE_FOR_xop_pcmov_v8df512 = 2667,
  CODE_FOR_xop_pcmov_v4df256 = 2668,
  CODE_FOR_xop_pcmov_v2df = 2669,
  CODE_FOR_xop_phaddbw = 2670,
  CODE_FOR_xop_phaddubw = 2671,
  CODE_FOR_xop_phaddbd = 2672,
  CODE_FOR_xop_phaddubd = 2673,
  CODE_FOR_xop_phaddbq = 2674,
  CODE_FOR_xop_phaddubq = 2675,
  CODE_FOR_xop_phaddwd = 2676,
  CODE_FOR_xop_phadduwd = 2677,
  CODE_FOR_xop_phaddwq = 2678,
  CODE_FOR_xop_phadduwq = 2679,
  CODE_FOR_xop_phadddq = 2680,
  CODE_FOR_xop_phaddudq = 2681,
  CODE_FOR_xop_phsubbw = 2682,
  CODE_FOR_xop_phsubwd = 2683,
  CODE_FOR_xop_phsubdq = 2684,
  CODE_FOR_xop_pperm = 2685,
  CODE_FOR_xop_pperm_pack_v2di_v4si = 2686,
  CODE_FOR_xop_pperm_pack_v4si_v8hi = 2687,
  CODE_FOR_xop_pperm_pack_v8hi_v16qi = 2688,
  CODE_FOR_xop_rotlv16qi3 = 2689,
  CODE_FOR_xop_rotlv8hi3 = 2690,
  CODE_FOR_xop_rotlv4si3 = 2691,
  CODE_FOR_xop_rotlv2di3 = 2692,
  CODE_FOR_xop_rotrv16qi3 = 2693,
  CODE_FOR_xop_rotrv8hi3 = 2694,
  CODE_FOR_xop_rotrv4si3 = 2695,
  CODE_FOR_xop_rotrv2di3 = 2696,
  CODE_FOR_xop_vrotlv16qi3 = 2697,
  CODE_FOR_xop_vrotlv8hi3 = 2698,
  CODE_FOR_xop_vrotlv4si3 = 2699,
  CODE_FOR_xop_vrotlv2di3 = 2700,
  CODE_FOR_xop_shav16qi3 = 2701,
  CODE_FOR_xop_shav8hi3 = 2702,
  CODE_FOR_xop_shav4si3 = 2703,
  CODE_FOR_xop_shav2di3 = 2704,
  CODE_FOR_xop_shlv16qi3 = 2705,
  CODE_FOR_xop_shlv8hi3 = 2706,
  CODE_FOR_xop_shlv4si3 = 2707,
  CODE_FOR_xop_shlv2di3 = 2708,
  CODE_FOR_xop_frczsf2 = 2709,
  CODE_FOR_xop_frczdf2 = 2710,
  CODE_FOR_xop_frczv4sf2 = 2711,
  CODE_FOR_xop_frczv2df2 = 2712,
  CODE_FOR_xop_frczv8sf2 = 2713,
  CODE_FOR_xop_frczv4df2 = 2714,
  CODE_FOR_xop_frczv16sf2 = 2715,
  CODE_FOR_xop_frczv8df2 = 2716,
  CODE_FOR_xop_maskcmpv16qi3 = 2719,
  CODE_FOR_xop_maskcmpv8hi3 = 2720,
  CODE_FOR_xop_maskcmpv4si3 = 2721,
  CODE_FOR_xop_maskcmpv2di3 = 2722,
  CODE_FOR_xop_maskcmp_unsv16qi3 = 2723,
  CODE_FOR_xop_maskcmp_unsv8hi3 = 2724,
  CODE_FOR_xop_maskcmp_unsv4si3 = 2725,
  CODE_FOR_xop_maskcmp_unsv2di3 = 2726,
  CODE_FOR_xop_maskcmp_uns2v16qi3 = 2727,
  CODE_FOR_xop_maskcmp_uns2v8hi3 = 2728,
  CODE_FOR_xop_maskcmp_uns2v4si3 = 2729,
  CODE_FOR_xop_maskcmp_uns2v2di3 = 2730,
  CODE_FOR_xop_pcom_tfv16qi3 = 2731,
  CODE_FOR_xop_pcom_tfv8hi3 = 2732,
  CODE_FOR_xop_pcom_tfv4si3 = 2733,
  CODE_FOR_xop_pcom_tfv2di3 = 2734,
  CODE_FOR_xop_vpermil2v8sf3 = 2735,
  CODE_FOR_xop_vpermil2v4sf3 = 2736,
  CODE_FOR_xop_vpermil2v4df3 = 2737,
  CODE_FOR_xop_vpermil2v2df3 = 2738,
  CODE_FOR_aesenc = 2739,
  CODE_FOR_aesenclast = 2740,
  CODE_FOR_aesdec = 2741,
  CODE_FOR_aesdeclast = 2742,
  CODE_FOR_aesimc = 2743,
  CODE_FOR_aeskeygenassist = 2744,
  CODE_FOR_pclmulqdq = 2745,
  CODE_FOR_avx_vzeroupper = 2747,
  CODE_FOR_avx2_pbroadcastv16si = 2748,
  CODE_FOR_avx2_pbroadcastv8di = 2749,
  CODE_FOR_avx2_pbroadcastv32qi = 2750,
  CODE_FOR_avx2_pbroadcastv16qi = 2751,
  CODE_FOR_avx2_pbroadcastv16hi = 2752,
  CODE_FOR_avx2_pbroadcastv8hi = 2753,
  CODE_FOR_avx2_pbroadcastv8si = 2754,
  CODE_FOR_avx2_pbroadcastv4si = 2755,
  CODE_FOR_avx2_pbroadcastv4di = 2756,
  CODE_FOR_avx2_pbroadcastv2di = 2757,
  CODE_FOR_avx2_pbroadcastv32qi_1 = 2758,
  CODE_FOR_avx2_pbroadcastv16hi_1 = 2759,
  CODE_FOR_avx2_pbroadcastv8si_1 = 2760,
  CODE_FOR_avx2_pbroadcastv4di_1 = 2761,
  CODE_FOR_avx2_permvarv8si = 2762,
#define CODE_FOR_avx2_permvarv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_permvarv8sf = 2763,
#define CODE_FOR_avx2_permvarv8sf_mask CODE_FOR_nothing
  CODE_FOR_avx512f_permvarv16si = 2764,
  CODE_FOR_avx512f_permvarv16si_mask = 2765,
  CODE_FOR_avx512f_permvarv16sf = 2766,
  CODE_FOR_avx512f_permvarv16sf_mask = 2767,
  CODE_FOR_avx512f_permvarv8di = 2768,
  CODE_FOR_avx512f_permvarv8di_mask = 2769,
  CODE_FOR_avx512f_permvarv8df = 2770,
  CODE_FOR_avx512f_permvarv8df_mask = 2771,
  CODE_FOR_avx2_permv4di_1 = 2772,
#define CODE_FOR_avx2_permv4di_1_mask CODE_FOR_nothing
  CODE_FOR_avx2_permv4df_1 = 2773,
#define CODE_FOR_avx2_permv4df_1_mask CODE_FOR_nothing
  CODE_FOR_avx512f_permv8di_1 = 2774,
  CODE_FOR_avx512f_permv8di_1_mask = 2775,
  CODE_FOR_avx512f_permv8df_1 = 2776,
  CODE_FOR_avx512f_permv8df_1_mask = 2777,
  CODE_FOR_avx2_permv2ti = 2778,
  CODE_FOR_avx2_vec_dupv4df = 2779,
  CODE_FOR_vec_dupv8si = 2780,
  CODE_FOR_vec_dupv8sf = 2781,
  CODE_FOR_vec_dupv4di = 2782,
  CODE_FOR_vec_dupv4df = 2783,
  CODE_FOR_avx512f_vec_dupv16si_mask = 2785,
  CODE_FOR_avx512f_vec_dupv16sf_mask = 2787,
  CODE_FOR_avx512f_vec_dupv8di_mask = 2789,
  CODE_FOR_avx512f_vec_dupv8df_mask = 2791,
  CODE_FOR_avx512f_broadcastv16sf_mask = 2793,
  CODE_FOR_avx512f_broadcastv16si_mask = 2795,
  CODE_FOR_avx512f_broadcastv8df_mask = 2797,
  CODE_FOR_avx512f_broadcastv8di_mask = 2799,
  CODE_FOR_avx512f_vec_dup_gprv16si_mask = 2801,
  CODE_FOR_avx512f_vec_dup_gprv8di_mask = 2803,
  CODE_FOR_avx512f_vec_dup_memv16si_mask = 2805,
  CODE_FOR_avx512f_vec_dup_memv16sf_mask = 2807,
  CODE_FOR_avx512f_vec_dup_memv8di_mask = 2809,
  CODE_FOR_avx512f_vec_dup_memv8df_mask = 2811,
  CODE_FOR_avx2_vbroadcasti128_v32qi = 2812,
  CODE_FOR_avx2_vbroadcasti128_v16hi = 2813,
  CODE_FOR_avx2_vbroadcasti128_v8si = 2814,
  CODE_FOR_avx2_vbroadcasti128_v4di = 2815,
  CODE_FOR_avx_vbroadcastf128_v32qi = 2816,
  CODE_FOR_avx_vbroadcastf128_v16hi = 2817,
  CODE_FOR_avx_vbroadcastf128_v8si = 2818,
  CODE_FOR_avx_vbroadcastf128_v4di = 2819,
  CODE_FOR_avx_vbroadcastf128_v8sf = 2820,
  CODE_FOR_avx_vbroadcastf128_v4df = 2821,
  CODE_FOR_avx512cd_maskb_vec_dupv8di = 2822,
  CODE_FOR_avx512cd_maskw_vec_dupv16si = 2823,
  CODE_FOR_avx512f_vpermilvarv16sf3 = 2835,
  CODE_FOR_avx512f_vpermilvarv16sf3_mask = 2836,
  CODE_FOR_avx_vpermilvarv8sf3 = 2837,
#define CODE_FOR_avx_vpermilvarv8sf3_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilvarv4sf3 = 2838,
#define CODE_FOR_avx_vpermilvarv4sf3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermilvarv8df3 = 2839,
  CODE_FOR_avx512f_vpermilvarv8df3_mask = 2840,
  CODE_FOR_avx_vpermilvarv4df3 = 2841,
#define CODE_FOR_avx_vpermilvarv4df3_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilvarv2df3 = 2842,
#define CODE_FOR_avx_vpermilvarv2df3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermi2varv16si3 = 2843,
  CODE_FOR_avx512f_vpermi2varv16si3_maskz_1 = 2844,
  CODE_FOR_avx512f_vpermi2varv16sf3 = 2845,
  CODE_FOR_avx512f_vpermi2varv16sf3_maskz_1 = 2846,
  CODE_FOR_avx512f_vpermi2varv8di3 = 2847,
  CODE_FOR_avx512f_vpermi2varv8di3_maskz_1 = 2848,
  CODE_FOR_avx512f_vpermi2varv8df3 = 2849,
  CODE_FOR_avx512f_vpermi2varv8df3_maskz_1 = 2850,
  CODE_FOR_avx512f_vpermi2varv16si3_mask = 2851,
  CODE_FOR_avx512f_vpermi2varv16sf3_mask = 2852,
  CODE_FOR_avx512f_vpermi2varv8di3_mask = 2853,
  CODE_FOR_avx512f_vpermi2varv8df3_mask = 2854,
  CODE_FOR_avx512f_vpermt2varv16si3 = 2855,
  CODE_FOR_avx512f_vpermt2varv16si3_maskz_1 = 2856,
  CODE_FOR_avx512f_vpermt2varv16sf3 = 2857,
  CODE_FOR_avx512f_vpermt2varv16sf3_maskz_1 = 2858,
  CODE_FOR_avx512f_vpermt2varv8di3 = 2859,
  CODE_FOR_avx512f_vpermt2varv8di3_maskz_1 = 2860,
  CODE_FOR_avx512f_vpermt2varv8df3 = 2861,
  CODE_FOR_avx512f_vpermt2varv8df3_maskz_1 = 2862,
  CODE_FOR_avx512f_vpermt2varv16si3_mask = 2863,
  CODE_FOR_avx512f_vpermt2varv16sf3_mask = 2864,
  CODE_FOR_avx512f_vpermt2varv8di3_mask = 2865,
  CODE_FOR_avx512f_vpermt2varv8df3_mask = 2866,
  CODE_FOR_avx2_vec_set_lo_v4di = 2873,
  CODE_FOR_avx2_vec_set_hi_v4di = 2874,
  CODE_FOR_vec_set_lo_v4di = 2875,
  CODE_FOR_vec_set_lo_v4df = 2876,
  CODE_FOR_vec_set_hi_v4di = 2877,
  CODE_FOR_vec_set_hi_v4df = 2878,
  CODE_FOR_vec_set_lo_v8si = 2879,
  CODE_FOR_vec_set_lo_v8sf = 2880,
  CODE_FOR_vec_set_hi_v8si = 2881,
  CODE_FOR_vec_set_hi_v8sf = 2882,
  CODE_FOR_vec_set_lo_v16hi = 2883,
  CODE_FOR_vec_set_hi_v16hi = 2884,
  CODE_FOR_vec_set_lo_v32qi = 2885,
  CODE_FOR_vec_set_hi_v32qi = 2886,
  CODE_FOR_avx_maskloadps = 2887,
  CODE_FOR_avx_maskloadpd = 2888,
  CODE_FOR_avx_maskloadps256 = 2889,
  CODE_FOR_avx_maskloadpd256 = 2890,
  CODE_FOR_avx2_maskloadd = 2891,
  CODE_FOR_avx2_maskloadq = 2892,
  CODE_FOR_avx2_maskloadd256 = 2893,
  CODE_FOR_avx2_maskloadq256 = 2894,
  CODE_FOR_avx_maskstoreps = 2895,
  CODE_FOR_avx_maskstorepd = 2896,
  CODE_FOR_avx_maskstoreps256 = 2897,
  CODE_FOR_avx_maskstorepd256 = 2898,
  CODE_FOR_avx2_maskstored = 2899,
  CODE_FOR_avx2_maskstoreq = 2900,
  CODE_FOR_avx2_maskstored256 = 2901,
  CODE_FOR_avx2_maskstoreq256 = 2902,
  CODE_FOR_avx_si256_si = 2903,
  CODE_FOR_avx_ps256_ps = 2904,
  CODE_FOR_avx_pd256_pd = 2905,
  CODE_FOR_avx512f_ashrvv16si = 2906,
  CODE_FOR_avx512f_ashrvv16si_mask = 2907,
  CODE_FOR_avx2_ashrvv8si = 2908,
#define CODE_FOR_avx2_ashrvv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_ashrvv4si = 2909,
#define CODE_FOR_avx2_ashrvv4si_mask CODE_FOR_nothing
  CODE_FOR_avx512f_ashrvv8di = 2910,
  CODE_FOR_avx512f_ashrvv8di_mask = 2911,
  CODE_FOR_avx512f_ashlvv16si = 2912,
  CODE_FOR_avx512f_ashlvv16si_mask = 2913,
  CODE_FOR_avx512f_lshrvv16si = 2914,
  CODE_FOR_avx512f_lshrvv16si_mask = 2915,
  CODE_FOR_avx2_ashlvv8si = 2916,
#define CODE_FOR_avx2_ashlvv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv8si = 2917,
#define CODE_FOR_avx2_lshrvv8si_mask CODE_FOR_nothing
  CODE_FOR_avx2_ashlvv4si = 2918,
#define CODE_FOR_avx2_ashlvv4si_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv4si = 2919,
#define CODE_FOR_avx2_lshrvv4si_mask CODE_FOR_nothing
  CODE_FOR_avx512f_ashlvv8di = 2920,
  CODE_FOR_avx512f_ashlvv8di_mask = 2921,
  CODE_FOR_avx512f_lshrvv8di = 2922,
  CODE_FOR_avx512f_lshrvv8di_mask = 2923,
  CODE_FOR_avx2_ashlvv4di = 2924,
#define CODE_FOR_avx2_ashlvv4di_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv4di = 2925,
#define CODE_FOR_avx2_lshrvv4di_mask CODE_FOR_nothing
  CODE_FOR_avx2_ashlvv2di = 2926,
#define CODE_FOR_avx2_ashlvv2di_mask CODE_FOR_nothing
  CODE_FOR_avx2_lshrvv2di = 2927,
#define CODE_FOR_avx2_lshrvv2di_mask CODE_FOR_nothing
  CODE_FOR_avx_vec_concatv32qi = 2928,
  CODE_FOR_avx_vec_concatv16hi = 2929,
  CODE_FOR_avx_vec_concatv8si = 2930,
  CODE_FOR_avx_vec_concatv4di = 2931,
  CODE_FOR_avx_vec_concatv8sf = 2932,
  CODE_FOR_avx_vec_concatv4df = 2933,
  CODE_FOR_avx_vec_concatv64qi = 2934,
  CODE_FOR_avx_vec_concatv32hi = 2935,
  CODE_FOR_avx_vec_concatv16si = 2936,
  CODE_FOR_avx_vec_concatv8di = 2937,
  CODE_FOR_avx_vec_concatv16sf = 2938,
  CODE_FOR_avx_vec_concatv8df = 2939,
  CODE_FOR_vcvtph2ps = 2940,
  CODE_FOR_vcvtph2ps256 = 2942,
  CODE_FOR_avx512f_vcvtph2ps512_mask = 2945,
  CODE_FOR_avx512f_vcvtph2ps512_mask_round = 2946,
  CODE_FOR_vcvtps2ph256 = 2949,
  CODE_FOR_avx512f_vcvtps2ph512_mask = 2951,
  CODE_FOR_avx512f_compressv16si_mask = 3072,
  CODE_FOR_avx512f_compressv16sf_mask = 3073,
  CODE_FOR_avx512f_compressv8di_mask = 3074,
  CODE_FOR_avx512f_compressv8df_mask = 3075,
  CODE_FOR_avx512f_compressstorev16si_mask = 3076,
  CODE_FOR_avx512f_compressstorev16sf_mask = 3077,
  CODE_FOR_avx512f_compressstorev8di_mask = 3078,
  CODE_FOR_avx512f_compressstorev8df_mask = 3079,
  CODE_FOR_avx512f_expandv16si_mask = 3080,
  CODE_FOR_avx512f_expandv16sf_mask = 3081,
  CODE_FOR_avx512f_expandv8di_mask = 3082,
  CODE_FOR_avx512f_expandv8df_mask = 3083,
  CODE_FOR_avx512f_getmantv16sf = 3084,
  CODE_FOR_avx512f_getmantv16sf_round = 3085,
  CODE_FOR_avx512f_getmantv16sf_mask = 3086,
  CODE_FOR_avx512f_getmantv16sf_mask_round = 3087,
  CODE_FOR_avx512f_getmantv8df = 3088,
  CODE_FOR_avx512f_getmantv8df_round = 3089,
  CODE_FOR_avx512f_getmantv8df_mask = 3090,
  CODE_FOR_avx512f_getmantv8df_mask_round = 3091,
  CODE_FOR_avx512f_getmantv4sf = 3092,
  CODE_FOR_avx512f_getmantv4sf_round = 3093,
  CODE_FOR_avx512f_getmantv2df = 3094,
  CODE_FOR_avx512f_getmantv2df_round = 3095,
  CODE_FOR_clzv16si2 = 3096,
  CODE_FOR_clzv16si2_mask = 3097,
  CODE_FOR_clzv8di2 = 3098,
  CODE_FOR_clzv8di2_mask = 3099,
  CODE_FOR_conflictv16si_mask = 3101,
  CODE_FOR_conflictv8di_mask = 3103,
  CODE_FOR_sha1msg1 = 3104,
  CODE_FOR_sha1msg2 = 3105,
  CODE_FOR_sha1nexte = 3106,
  CODE_FOR_sha1rnds4 = 3107,
  CODE_FOR_sha256msg1 = 3108,
  CODE_FOR_sha256msg2 = 3109,
  CODE_FOR_sha256rnds2 = 3110,
  CODE_FOR_mfence_sse2 = 3113,
  CODE_FOR_mfence_nosse = 3114,
  CODE_FOR_atomic_loaddi_fpu = 3115,
  CODE_FOR_atomic_storeqi_1 = 3116,
  CODE_FOR_atomic_storehi_1 = 3117,
  CODE_FOR_atomic_storesi_1 = 3118,
  CODE_FOR_atomic_storedi_1 = 3119,
  CODE_FOR_atomic_storedi_fpu = 3120,
  CODE_FOR_loaddi_via_fpu = 3121,
  CODE_FOR_storedi_via_fpu = 3122,
  CODE_FOR_atomic_compare_and_swapqi_1 = 3123,
  CODE_FOR_atomic_compare_and_swaphi_1 = 3124,
  CODE_FOR_atomic_compare_and_swapsi_1 = 3125,
  CODE_FOR_atomic_compare_and_swapdi_1 = 3126,
  CODE_FOR_atomic_compare_and_swapdi_doubleword = 3127,
  CODE_FOR_atomic_compare_and_swapti_doubleword = 3128,
  CODE_FOR_atomic_fetch_addqi = 3129,
  CODE_FOR_atomic_fetch_addhi = 3130,
  CODE_FOR_atomic_fetch_addsi = 3131,
  CODE_FOR_atomic_fetch_adddi = 3132,
  CODE_FOR_atomic_exchangeqi = 3137,
  CODE_FOR_atomic_exchangehi = 3138,
  CODE_FOR_atomic_exchangesi = 3139,
  CODE_FOR_atomic_exchangedi = 3140,
  CODE_FOR_atomic_addqi = 3141,
  CODE_FOR_atomic_addhi = 3142,
  CODE_FOR_atomic_addsi = 3143,
  CODE_FOR_atomic_adddi = 3144,
  CODE_FOR_atomic_subqi = 3145,
  CODE_FOR_atomic_subhi = 3146,
  CODE_FOR_atomic_subsi = 3147,
  CODE_FOR_atomic_subdi = 3148,
  CODE_FOR_atomic_andqi = 3149,
  CODE_FOR_atomic_orqi = 3150,
  CODE_FOR_atomic_xorqi = 3151,
  CODE_FOR_atomic_andhi = 3152,
  CODE_FOR_atomic_orhi = 3153,
  CODE_FOR_atomic_xorhi = 3154,
  CODE_FOR_atomic_andsi = 3155,
  CODE_FOR_atomic_orsi = 3156,
  CODE_FOR_atomic_xorsi = 3157,
  CODE_FOR_atomic_anddi = 3158,
  CODE_FOR_atomic_ordi = 3159,
  CODE_FOR_atomic_xordi = 3160,
  CODE_FOR_cbranchqi4 = 3161,
  CODE_FOR_cbranchhi4 = 3162,
  CODE_FOR_cbranchsi4 = 3163,
  CODE_FOR_cbranchdi4 = 3164,
  CODE_FOR_cbranchti4 = 3165,
  CODE_FOR_cstoreqi4 = 3166,
  CODE_FOR_cstorehi4 = 3167,
  CODE_FOR_cstoresi4 = 3168,
  CODE_FOR_cstoredi4 = 3169,
  CODE_FOR_cmpsi_1 = 3170,
  CODE_FOR_cmpdi_1 = 3171,
  CODE_FOR_cmpqi_ext_3 = 3172,
  CODE_FOR_cbranchxf4 = 3173,
  CODE_FOR_cstorexf4 = 3174,
  CODE_FOR_cbranchsf4 = 3175,
  CODE_FOR_cbranchdf4 = 3176,
  CODE_FOR_cstoresf4 = 3177,
  CODE_FOR_cstoredf4 = 3178,
  CODE_FOR_cbranchcc4 = 3179,
  CODE_FOR_cstorecc4 = 3180,
  CODE_FOR_movxi = 3201,
  CODE_FOR_reload_noff_store = 3202,
  CODE_FOR_reload_noff_load = 3203,
  CODE_FOR_movoi = 3204,
  CODE_FOR_movti = 3205,
  CODE_FOR_movcdi = 3206,
  CODE_FOR_movqi = 3207,
  CODE_FOR_movhi = 3208,
  CODE_FOR_movsi = 3209,
  CODE_FOR_movdi = 3210,
  CODE_FOR_movstrictqi = 3213,
  CODE_FOR_movstricthi = 3214,
  CODE_FOR_movtf = 3225,
  CODE_FOR_movsf = 3226,
  CODE_FOR_movdf = 3227,
  CODE_FOR_movxf = 3228,
  CODE_FOR_zero_extendsidi2 = 3235,
  CODE_FOR_zero_extendqisi2 = 3239,
  CODE_FOR_zero_extendhisi2 = 3240,
  CODE_FOR_zero_extendqihi2 = 3243,
  CODE_FOR_extendsidi2 = 3245,
  CODE_FOR_extendsfdf2 = 3256,
  CODE_FOR_extendsfxf2 = 3259,
  CODE_FOR_extenddfxf2 = 3260,
  CODE_FOR_truncdfsf2 = 3261,
  CODE_FOR_truncdfsf2_with_temp = 3264,
  CODE_FOR_truncxfsf2 = 3266,
  CODE_FOR_truncxfdf2 = 3267,
  CODE_FOR_fix_truncxfdi2 = 3272,
  CODE_FOR_fix_truncsfdi2 = 3273,
  CODE_FOR_fix_truncdfdi2 = 3274,
  CODE_FOR_fix_truncxfsi2 = 3275,
  CODE_FOR_fix_truncsfsi2 = 3276,
  CODE_FOR_fix_truncdfsi2 = 3277,
  CODE_FOR_fix_truncsfhi2 = 3278,
  CODE_FOR_fix_truncdfhi2 = 3279,
  CODE_FOR_fix_truncxfhi2 = 3280,
  CODE_FOR_fixuns_truncsfsi2 = 3281,
  CODE_FOR_fixuns_truncdfsi2 = 3282,
  CODE_FOR_fixuns_truncsfhi2 = 3285,
  CODE_FOR_fixuns_truncdfhi2 = 3286,
  CODE_FOR_floatsisf2 = 3309,
  CODE_FOR_floatdisf2 = 3310,
  CODE_FOR_floatsidf2 = 3311,
  CODE_FOR_floatdidf2 = 3312,
  CODE_FOR_floatunsqisf2 = 3327,
  CODE_FOR_floatunshisf2 = 3328,
  CODE_FOR_floatunsqidf2 = 3329,
  CODE_FOR_floatunshidf2 = 3330,
  CODE_FOR_floatunssisf2 = 3337,
  CODE_FOR_floatunssidf2 = 3338,
  CODE_FOR_floatunssixf2 = 3339,
  CODE_FOR_floatunsdisf2 = 3340,
  CODE_FOR_floatunsdidf2 = 3341,
  CODE_FOR_addqi3 = 3344,
  CODE_FOR_addhi3 = 3345,
  CODE_FOR_addsi3 = 3346,
  CODE_FOR_adddi3 = 3347,
  CODE_FOR_addti3 = 3348,
  CODE_FOR_addvqi4 = 3359,
  CODE_FOR_addvhi4 = 3360,
  CODE_FOR_addvsi4 = 3361,
  CODE_FOR_addvdi4 = 3362,
  CODE_FOR_subqi3 = 3368,
  CODE_FOR_subhi3 = 3369,
  CODE_FOR_subsi3 = 3370,
  CODE_FOR_subdi3 = 3371,
  CODE_FOR_subti3 = 3372,
  CODE_FOR_subvqi4 = 3375,
  CODE_FOR_subvhi4 = 3376,
  CODE_FOR_subvsi4 = 3377,
  CODE_FOR_subvdi4 = 3378,
  CODE_FOR_addqi3_carry = 3379,
  CODE_FOR_subqi3_carry = 3380,
  CODE_FOR_addhi3_carry = 3381,
  CODE_FOR_subhi3_carry = 3382,
  CODE_FOR_addsi3_carry = 3383,
  CODE_FOR_subsi3_carry = 3384,
  CODE_FOR_adddi3_carry = 3385,
  CODE_FOR_subdi3_carry = 3386,
  CODE_FOR_addxf3 = 3387,
  CODE_FOR_subxf3 = 3388,
  CODE_FOR_addsf3 = 3389,
  CODE_FOR_subsf3 = 3390,
  CODE_FOR_adddf3 = 3391,
  CODE_FOR_subdf3 = 3392,
  CODE_FOR_mulhi3 = 3393,
  CODE_FOR_mulsi3 = 3394,
  CODE_FOR_muldi3 = 3395,
  CODE_FOR_mulqi3 = 3396,
  CODE_FOR_mulvsi4 = 3397,
  CODE_FOR_mulvdi4 = 3398,
  CODE_FOR_mulsidi3 = 3399,
  CODE_FOR_umulsidi3 = 3400,
  CODE_FOR_mulditi3 = 3401,
  CODE_FOR_umulditi3 = 3402,
  CODE_FOR_mulqihi3 = 3403,
  CODE_FOR_umulqihi3 = 3404,
  CODE_FOR_smulsi3_highpart = 3407,
  CODE_FOR_umulsi3_highpart = 3408,
  CODE_FOR_smuldi3_highpart = 3409,
  CODE_FOR_umuldi3_highpart = 3410,
  CODE_FOR_mulxf3 = 3411,
  CODE_FOR_mulsf3 = 3412,
  CODE_FOR_muldf3 = 3413,
  CODE_FOR_divxf3 = 3414,
  CODE_FOR_divdf3 = 3415,
  CODE_FOR_divsf3 = 3416,
  CODE_FOR_divmodhi4 = 3417,
  CODE_FOR_divmodsi4 = 3418,
  CODE_FOR_divmoddi4 = 3419,
  CODE_FOR_divmodqi4 = 3427,
  CODE_FOR_udivmodhi4 = 3428,
  CODE_FOR_udivmodsi4 = 3429,
  CODE_FOR_udivmoddi4 = 3430,
  CODE_FOR_udivmodqi4 = 3438,
  CODE_FOR_testsi_ccno_1 = 3439,
  CODE_FOR_testqi_ccz_1 = 3440,
  CODE_FOR_testdi_ccno_1 = 3441,
  CODE_FOR_testqi_ext_ccno_0 = 3442,
  CODE_FOR_andqi3 = 3452,
  CODE_FOR_andhi3 = 3453,
  CODE_FOR_andsi3 = 3454,
  CODE_FOR_anddi3 = 3455,
  CODE_FOR_iorqi3 = 3467,
  CODE_FOR_xorqi3 = 3468,
  CODE_FOR_iorhi3 = 3469,
  CODE_FOR_xorhi3 = 3470,
  CODE_FOR_iorsi3 = 3471,
  CODE_FOR_xorsi3 = 3472,
  CODE_FOR_iordi3 = 3473,
  CODE_FOR_xordi3 = 3474,
  CODE_FOR_xorqi_cc_ext_1 = 3481,
  CODE_FOR_negqi2 = 3482,
  CODE_FOR_neghi2 = 3483,
  CODE_FOR_negsi2 = 3484,
  CODE_FOR_negdi2 = 3485,
  CODE_FOR_negti2 = 3486,
  CODE_FOR_negvqi3 = 3489,
  CODE_FOR_negvhi3 = 3490,
  CODE_FOR_negvsi3 = 3491,
  CODE_FOR_negvdi3 = 3492,
  CODE_FOR_abssf2 = 3493,
  CODE_FOR_negsf2 = 3494,
  CODE_FOR_absdf2 = 3495,
  CODE_FOR_negdf2 = 3496,
  CODE_FOR_absxf2 = 3497,
  CODE_FOR_negxf2 = 3498,
  CODE_FOR_abstf2 = 3499,
  CODE_FOR_negtf2 = 3500,
  CODE_FOR_copysignsf3 = 3506,
  CODE_FOR_copysigndf3 = 3507,
  CODE_FOR_copysigntf3 = 3508,
  CODE_FOR_one_cmplqi2 = 3515,
  CODE_FOR_one_cmplhi2 = 3516,
  CODE_FOR_one_cmplsi2 = 3517,
  CODE_FOR_one_cmpldi2 = 3518,
  CODE_FOR_ashlqi3 = 3524,
  CODE_FOR_ashlhi3 = 3525,
  CODE_FOR_ashlsi3 = 3526,
  CODE_FOR_ashldi3 = 3527,
  CODE_FOR_ashlti3 = 3528,
  CODE_FOR_x86_shiftsi_adj_1 = 3533,
  CODE_FOR_x86_shiftdi_adj_1 = 3534,
  CODE_FOR_x86_shiftsi_adj_2 = 3535,
  CODE_FOR_x86_shiftdi_adj_2 = 3536,
  CODE_FOR_lshrqi3 = 3542,
  CODE_FOR_ashrqi3 = 3543,
  CODE_FOR_lshrhi3 = 3544,
  CODE_FOR_ashrhi3 = 3545,
  CODE_FOR_lshrsi3 = 3546,
  CODE_FOR_ashrsi3 = 3547,
  CODE_FOR_lshrdi3 = 3548,
  CODE_FOR_ashrdi3 = 3549,
  CODE_FOR_lshrti3 = 3550,
  CODE_FOR_ashrti3 = 3551,
  CODE_FOR_x86_shiftsi_adj_3 = 3560,
  CODE_FOR_x86_shiftdi_adj_3 = 3561,
  CODE_FOR_rotlti3 = 3568,
  CODE_FOR_rotrti3 = 3569,
  CODE_FOR_rotldi3 = 3570,
  CODE_FOR_rotrdi3 = 3571,
  CODE_FOR_rotlqi3 = 3572,
  CODE_FOR_rotrqi3 = 3573,
  CODE_FOR_rotlhi3 = 3574,
  CODE_FOR_rotrhi3 = 3575,
  CODE_FOR_rotlsi3 = 3576,
  CODE_FOR_rotrsi3 = 3577,
  CODE_FOR_extv = 3590,
  CODE_FOR_extzv = 3591,
  CODE_FOR_insv = 3592,
  CODE_FOR_indirect_jump = 3625,
  CODE_FOR_tablejump = 3626,
  CODE_FOR_call = 3631,
  CODE_FOR_sibcall = 3632,
  CODE_FOR_call_pop = 3633,
  CODE_FOR_call_value = 3634,
  CODE_FOR_sibcall_value = 3635,
  CODE_FOR_call_value_pop = 3636,
  CODE_FOR_untyped_call = 3637,
  CODE_FOR_memory_blockage = 3638,
  CODE_FOR_return = 3639,
  CODE_FOR_simple_return = 3640,
  CODE_FOR_prologue = 3641,
  CODE_FOR_epilogue = 3642,
  CODE_FOR_sibcall_epilogue = 3643,
  CODE_FOR_eh_return = 3644,
  CODE_FOR_split_stack_prologue = 3646,
  CODE_FOR_split_stack_space_check = 3647,
  CODE_FOR_ffssi2 = 3648,
  CODE_FOR_ffsdi2 = 3649,
  CODE_FOR_clzhi2 = 3651,
  CODE_FOR_clzsi2 = 3652,
  CODE_FOR_clzdi2 = 3653,
  CODE_FOR_bswapdi2 = 3654,
  CODE_FOR_bswapsi2 = 3655,
  CODE_FOR_paritydi2 = 3656,
  CODE_FOR_paritysi2 = 3657,
  CODE_FOR_tls_global_dynamic_32 = 3660,
  CODE_FOR_tls_global_dynamic_64_si = 3661,
  CODE_FOR_tls_global_dynamic_64_di = 3662,
  CODE_FOR_tls_local_dynamic_base_32 = 3663,
  CODE_FOR_tls_local_dynamic_base_64_si = 3664,
  CODE_FOR_tls_local_dynamic_base_64_di = 3665,
  CODE_FOR_tls_dynamic_gnu2_32 = 3667,
  CODE_FOR_tls_dynamic_gnu2_64 = 3669,
  CODE_FOR_rsqrtsf2 = 3671,
  CODE_FOR_sqrtsf2 = 3672,
  CODE_FOR_sqrtdf2 = 3673,
  CODE_FOR_fmodxf3 = 3674,
  CODE_FOR_fmodsf3 = 3675,
  CODE_FOR_fmoddf3 = 3676,
  CODE_FOR_remainderxf3 = 3677,
  CODE_FOR_remaindersf3 = 3678,
  CODE_FOR_remainderdf3 = 3679,
  CODE_FOR_sincossf3 = 3686,
  CODE_FOR_sincosdf3 = 3687,
  CODE_FOR_tanxf2 = 3688,
  CODE_FOR_tansf2 = 3689,
  CODE_FOR_tandf2 = 3690,
  CODE_FOR_atan2xf3 = 3691,
  CODE_FOR_atan2sf3 = 3692,
  CODE_FOR_atan2df3 = 3693,
  CODE_FOR_atanxf2 = 3694,
  CODE_FOR_atansf2 = 3695,
  CODE_FOR_atandf2 = 3696,
  CODE_FOR_asinxf2 = 3697,
  CODE_FOR_asinsf2 = 3698,
  CODE_FOR_asindf2 = 3699,
  CODE_FOR_acosxf2 = 3700,
  CODE_FOR_acossf2 = 3701,
  CODE_FOR_acosdf2 = 3702,
  CODE_FOR_logxf2 = 3703,
  CODE_FOR_logsf2 = 3704,
  CODE_FOR_logdf2 = 3705,
  CODE_FOR_log10xf2 = 3706,
  CODE_FOR_log10sf2 = 3707,
  CODE_FOR_log10df2 = 3708,
  CODE_FOR_log2xf2 = 3709,
  CODE_FOR_log2sf2 = 3710,
  CODE_FOR_log2df2 = 3711,
  CODE_FOR_log1pxf2 = 3712,
  CODE_FOR_log1psf2 = 3713,
  CODE_FOR_log1pdf2 = 3714,
  CODE_FOR_logbxf2 = 3715,
  CODE_FOR_logbsf2 = 3716,
  CODE_FOR_logbdf2 = 3717,
  CODE_FOR_ilogbxf2 = 3718,
  CODE_FOR_ilogbsf2 = 3719,
  CODE_FOR_ilogbdf2 = 3720,
  CODE_FOR_expNcorexf3 = 3721,
  CODE_FOR_expxf2 = 3722,
  CODE_FOR_expsf2 = 3723,
  CODE_FOR_expdf2 = 3724,
  CODE_FOR_exp10xf2 = 3725,
  CODE_FOR_exp10sf2 = 3726,
  CODE_FOR_exp10df2 = 3727,
  CODE_FOR_exp2xf2 = 3728,
  CODE_FOR_exp2sf2 = 3729,
  CODE_FOR_exp2df2 = 3730,
  CODE_FOR_expm1xf2 = 3731,
  CODE_FOR_expm1sf2 = 3732,
  CODE_FOR_expm1df2 = 3733,
  CODE_FOR_ldexpxf3 = 3734,
  CODE_FOR_ldexpsf3 = 3735,
  CODE_FOR_ldexpdf3 = 3736,
  CODE_FOR_scalbxf3 = 3737,
  CODE_FOR_scalbsf3 = 3738,
  CODE_FOR_scalbdf3 = 3739,
  CODE_FOR_significandxf2 = 3740,
  CODE_FOR_significandsf2 = 3741,
  CODE_FOR_significanddf2 = 3742,
  CODE_FOR_rintsf2 = 3743,
  CODE_FOR_rintdf2 = 3744,
  CODE_FOR_roundsf2 = 3745,
  CODE_FOR_rounddf2 = 3746,
  CODE_FOR_roundxf2 = 3747,
  CODE_FOR_lrintxfhi2 = 3757,
  CODE_FOR_lrintxfsi2 = 3758,
  CODE_FOR_lrintxfdi2 = 3759,
  CODE_FOR_lrintsfsi2 = 3760,
  CODE_FOR_lrintsfdi2 = 3761,
  CODE_FOR_lrintdfsi2 = 3762,
  CODE_FOR_lrintdfdi2 = 3763,
  CODE_FOR_lroundsfhi2 = 3764,
  CODE_FOR_lrounddfhi2 = 3765,
  CODE_FOR_lroundxfhi2 = 3766,
  CODE_FOR_lroundsfsi2 = 3767,
  CODE_FOR_lrounddfsi2 = 3768,
  CODE_FOR_lroundxfsi2 = 3769,
  CODE_FOR_lroundsfdi2 = 3770,
  CODE_FOR_lrounddfdi2 = 3771,
  CODE_FOR_lroundxfdi2 = 3772,
  CODE_FOR_floorxf2 = 3776,
  CODE_FOR_ceilxf2 = 3777,
  CODE_FOR_btruncxf2 = 3778,
  CODE_FOR_floorsf2 = 3779,
  CODE_FOR_ceilsf2 = 3780,
  CODE_FOR_btruncsf2 = 3781,
  CODE_FOR_floordf2 = 3782,
  CODE_FOR_ceildf2 = 3783,
  CODE_FOR_btruncdf2 = 3784,
  CODE_FOR_nearbyintxf2 = 3786,
  CODE_FOR_nearbyintsf2 = 3787,
  CODE_FOR_nearbyintdf2 = 3788,
  CODE_FOR_lfloorxfhi2 = 3807,
  CODE_FOR_lceilxfhi2 = 3808,
  CODE_FOR_lfloorxfsi2 = 3809,
  CODE_FOR_lceilxfsi2 = 3810,
  CODE_FOR_lfloorxfdi2 = 3811,
  CODE_FOR_lceilxfdi2 = 3812,
  CODE_FOR_lfloorsfsi2 = 3813,
  CODE_FOR_lceilsfsi2 = 3814,
  CODE_FOR_lfloorsfdi2 = 3815,
  CODE_FOR_lceilsfdi2 = 3816,
  CODE_FOR_lfloordfsi2 = 3817,
  CODE_FOR_lceildfsi2 = 3818,
  CODE_FOR_lfloordfdi2 = 3819,
  CODE_FOR_lceildfdi2 = 3820,
  CODE_FOR_isinfxf2 = 3823,
  CODE_FOR_isinfsf2 = 3824,
  CODE_FOR_isinfdf2 = 3825,
  CODE_FOR_signbitxf2 = 3826,
  CODE_FOR_signbitdf2 = 3827,
  CODE_FOR_signbitsf2 = 3828,
  CODE_FOR_movmemsi = 3829,
  CODE_FOR_movmemdi = 3830,
  CODE_FOR_strmov = 3831,
  CODE_FOR_strmov_singleop = 3832,
  CODE_FOR_rep_mov = 3833,
  CODE_FOR_setmemsi = 3834,
  CODE_FOR_setmemdi = 3835,
  CODE_FOR_strset = 3836,
  CODE_FOR_strset_singleop = 3837,
  CODE_FOR_rep_stos = 3838,
  CODE_FOR_cmpstrnsi = 3839,
  CODE_FOR_cmpintqi = 3840,
  CODE_FOR_cmpstrnqi_nz_1 = 3841,
  CODE_FOR_cmpstrnqi_1 = 3842,
  CODE_FOR_strlensi = 3843,
  CODE_FOR_strlendi = 3844,
  CODE_FOR_strlenqi_1 = 3845,
  CODE_FOR_movqicc = 3848,
  CODE_FOR_movhicc = 3849,
  CODE_FOR_movsicc = 3850,
  CODE_FOR_movdicc = 3851,
  CODE_FOR_x86_movsicc_0_m1 = 3852,
  CODE_FOR_x86_movdicc_0_m1 = 3853,
  CODE_FOR_movsfcc = 3865,
  CODE_FOR_movdfcc = 3866,
  CODE_FOR_movxfcc = 3867,
  CODE_FOR_addqicc = 3876,
  CODE_FOR_addhicc = 3877,
  CODE_FOR_addsicc = 3878,
  CODE_FOR_adddicc = 3879,
  CODE_FOR_allocate_stack = 3880,
  CODE_FOR_probe_stack = 3881,
  CODE_FOR_builtin_setjmp_receiver = 3882,
  CODE_FOR_prefetch = 3989,
  CODE_FOR_stack_protect_set = 3990,
  CODE_FOR_stack_protect_test = 3991,
  CODE_FOR_lwp_llwpcb = 3992,
  CODE_FOR_lwp_slwpcb = 3993,
  CODE_FOR_lwp_lwpvalsi3 = 3994,
  CODE_FOR_lwp_lwpvaldi3 = 3995,
  CODE_FOR_lwp_lwpinssi3 = 3996,
  CODE_FOR_lwp_lwpinsdi3 = 3997,
  CODE_FOR_pause = 3998,
  CODE_FOR_xbegin = 3999,
  CODE_FOR_xtest = 4000,
  CODE_FOR_movv8qi = 4001,
  CODE_FOR_movv4hi = 4002,
  CODE_FOR_movv2si = 4003,
  CODE_FOR_movv1di = 4004,
  CODE_FOR_movv2sf = 4005,
  CODE_FOR_movmisalignv8qi = 4011,
  CODE_FOR_movmisalignv4hi = 4012,
  CODE_FOR_movmisalignv2si = 4013,
  CODE_FOR_movmisalignv1di = 4014,
  CODE_FOR_movmisalignv2sf = 4015,
  CODE_FOR_mmx_addv2sf3 = 4016,
  CODE_FOR_mmx_subv2sf3 = 4017,
  CODE_FOR_mmx_subrv2sf3 = 4018,
  CODE_FOR_mmx_mulv2sf3 = 4019,
  CODE_FOR_mmx_smaxv2sf3 = 4020,
  CODE_FOR_mmx_sminv2sf3 = 4021,
  CODE_FOR_mmx_eqv2sf3 = 4022,
  CODE_FOR_vec_setv2sf = 4023,
  CODE_FOR_vec_extractv2sf = 4026,
  CODE_FOR_vec_initv2sf = 4027,
  CODE_FOR_mmx_addv8qi3 = 4028,
  CODE_FOR_mmx_subv8qi3 = 4029,
  CODE_FOR_mmx_addv4hi3 = 4030,
  CODE_FOR_mmx_subv4hi3 = 4031,
  CODE_FOR_mmx_addv2si3 = 4032,
  CODE_FOR_mmx_subv2si3 = 4033,
  CODE_FOR_mmx_addv1di3 = 4034,
  CODE_FOR_mmx_subv1di3 = 4035,
  CODE_FOR_mmx_ssaddv8qi3 = 4036,
  CODE_FOR_mmx_usaddv8qi3 = 4037,
  CODE_FOR_mmx_sssubv8qi3 = 4038,
  CODE_FOR_mmx_ussubv8qi3 = 4039,
  CODE_FOR_mmx_ssaddv4hi3 = 4040,
  CODE_FOR_mmx_usaddv4hi3 = 4041,
  CODE_FOR_mmx_sssubv4hi3 = 4042,
  CODE_FOR_mmx_ussubv4hi3 = 4043,
  CODE_FOR_mmx_mulv4hi3 = 4044,
  CODE_FOR_mmx_smulv4hi3_highpart = 4045,
  CODE_FOR_mmx_umulv4hi3_highpart = 4046,
  CODE_FOR_mmx_pmaddwd = 4047,
  CODE_FOR_mmx_pmulhrwv4hi3 = 4048,
  CODE_FOR_sse2_umulv1siv1di3 = 4049,
  CODE_FOR_mmx_smaxv4hi3 = 4050,
  CODE_FOR_mmx_sminv4hi3 = 4051,
  CODE_FOR_mmx_umaxv8qi3 = 4052,
  CODE_FOR_mmx_uminv8qi3 = 4053,
  CODE_FOR_mmx_eqv8qi3 = 4054,
  CODE_FOR_mmx_eqv4hi3 = 4055,
  CODE_FOR_mmx_eqv2si3 = 4056,
  CODE_FOR_mmx_andv8qi3 = 4057,
  CODE_FOR_mmx_iorv8qi3 = 4058,
  CODE_FOR_mmx_xorv8qi3 = 4059,
  CODE_FOR_mmx_andv4hi3 = 4060,
  CODE_FOR_mmx_iorv4hi3 = 4061,
  CODE_FOR_mmx_xorv4hi3 = 4062,
  CODE_FOR_mmx_andv2si3 = 4063,
  CODE_FOR_mmx_iorv2si3 = 4064,
  CODE_FOR_mmx_xorv2si3 = 4065,
  CODE_FOR_mmx_pinsrw = 4066,
  CODE_FOR_mmx_pshufw = 4067,
  CODE_FOR_vec_setv2si = 4068,
  CODE_FOR_vec_extractv2si = 4072,
  CODE_FOR_vec_initv2si = 4073,
  CODE_FOR_vec_setv4hi = 4074,
  CODE_FOR_vec_extractv4hi = 4075,
  CODE_FOR_vec_initv4hi = 4076,
  CODE_FOR_vec_setv8qi = 4077,
  CODE_FOR_vec_extractv8qi = 4078,
  CODE_FOR_vec_initv8qi = 4079,
  CODE_FOR_mmx_uavgv8qi3 = 4080,
  CODE_FOR_mmx_uavgv4hi3 = 4081,
  CODE_FOR_mmx_maskmovq = 4082,
  CODE_FOR_mmx_emms = 4083,
  CODE_FOR_mmx_femms = 4084,
  CODE_FOR_movv64qi = 4085,
  CODE_FOR_movv32qi = 4086,
  CODE_FOR_movv16qi = 4087,
  CODE_FOR_movv32hi = 4088,
  CODE_FOR_movv16hi = 4089,
  CODE_FOR_movv8hi = 4090,
  CODE_FOR_movv16si = 4091,
  CODE_FOR_movv8si = 4092,
  CODE_FOR_movv4si = 4093,
  CODE_FOR_movv8di = 4094,
  CODE_FOR_movv4di = 4095,
  CODE_FOR_movv2di = 4096,
  CODE_FOR_movv2ti = 4097,
  CODE_FOR_movv1ti = 4098,
  CODE_FOR_movv16sf = 4099,
  CODE_FOR_movv8sf = 4100,
  CODE_FOR_movv4sf = 4101,
  CODE_FOR_movv8df = 4102,
  CODE_FOR_movv4df = 4103,
  CODE_FOR_movv2df = 4104,
  CODE_FOR_movmisalignv64qi = 4108,
  CODE_FOR_movmisalignv32qi = 4109,
  CODE_FOR_movmisalignv16qi = 4110,
  CODE_FOR_movmisalignv32hi = 4111,
  CODE_FOR_movmisalignv16hi = 4112,
  CODE_FOR_movmisalignv8hi = 4113,
  CODE_FOR_movmisalignv16si = 4114,
  CODE_FOR_movmisalignv8si = 4115,
  CODE_FOR_movmisalignv4si = 4116,
  CODE_FOR_movmisalignv8di = 4117,
  CODE_FOR_movmisalignv4di = 4118,
  CODE_FOR_movmisalignv2di = 4119,
  CODE_FOR_movmisalignv2ti = 4120,
  CODE_FOR_movmisalignv1ti = 4121,
  CODE_FOR_movmisalignv16sf = 4122,
  CODE_FOR_movmisalignv8sf = 4123,
  CODE_FOR_movmisalignv4sf = 4124,
  CODE_FOR_movmisalignv8df = 4125,
  CODE_FOR_movmisalignv4df = 4126,
  CODE_FOR_movmisalignv2df = 4127,
  CODE_FOR_avx512f_loadups512 = 4128,
  CODE_FOR_avx512f_loadups512_mask = 4129,
  CODE_FOR_avx_loadups256 = 4130,
#define CODE_FOR_avx_loadups256_mask CODE_FOR_nothing
  CODE_FOR_sse_loadups = 4131,
#define CODE_FOR_sse_loadups_mask CODE_FOR_nothing
  CODE_FOR_avx512f_loadupd512 = 4132,
  CODE_FOR_avx512f_loadupd512_mask = 4133,
  CODE_FOR_avx_loadupd256 = 4134,
#define CODE_FOR_avx_loadupd256_mask CODE_FOR_nothing
  CODE_FOR_sse2_loadupd = 4135,
#define CODE_FOR_sse2_loadupd_mask CODE_FOR_nothing
  CODE_FOR_avx_loaddquv32qi = 4136,
  CODE_FOR_sse2_loaddquv16qi = 4137,
#define CODE_FOR_sse2_loaddquv16qi_mask CODE_FOR_nothing
  CODE_FOR_avx512f_loaddquv16si = 4138,
  CODE_FOR_avx512f_loaddquv16si_mask = 4139,
  CODE_FOR_avx512f_loaddquv8di = 4140,
  CODE_FOR_avx512f_loaddquv8di_mask = 4141,
  CODE_FOR_storentdi = 4142,
  CODE_FOR_storentsi = 4143,
  CODE_FOR_storentsf = 4144,
  CODE_FOR_storentdf = 4145,
  CODE_FOR_storentv8di = 4146,
  CODE_FOR_storentv4di = 4147,
  CODE_FOR_storentv2di = 4148,
  CODE_FOR_storentv16sf = 4149,
  CODE_FOR_storentv8sf = 4150,
  CODE_FOR_storentv4sf = 4151,
  CODE_FOR_storentv8df = 4152,
  CODE_FOR_storentv4df = 4153,
  CODE_FOR_storentv2df = 4154,
  CODE_FOR_absv16sf2 = 4155,
  CODE_FOR_negv16sf2 = 4156,
  CODE_FOR_absv8sf2 = 4157,
  CODE_FOR_negv8sf2 = 4158,
  CODE_FOR_absv4sf2 = 4159,
  CODE_FOR_negv4sf2 = 4160,
  CODE_FOR_absv8df2 = 4161,
  CODE_FOR_negv8df2 = 4162,
  CODE_FOR_absv4df2 = 4163,
  CODE_FOR_negv4df2 = 4164,
  CODE_FOR_absv2df2 = 4165,
  CODE_FOR_negv2df2 = 4166,
  CODE_FOR_addv16sf3 = 4173,
  CODE_FOR_addv16sf3_round = 4174,
  CODE_FOR_addv16sf3_mask = 4175,
  CODE_FOR_addv16sf3_mask_round = 4176,
  CODE_FOR_subv16sf3 = 4177,
  CODE_FOR_subv16sf3_round = 4178,
  CODE_FOR_subv16sf3_mask = 4179,
  CODE_FOR_subv16sf3_mask_round = 4180,
  CODE_FOR_addv8sf3 = 4181,
#define CODE_FOR_addv8sf3_round CODE_FOR_nothing
#define CODE_FOR_addv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_addv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_subv8sf3 = 4182,
#define CODE_FOR_subv8sf3_round CODE_FOR_nothing
#define CODE_FOR_subv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_subv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_addv4sf3 = 4183,
#define CODE_FOR_addv4sf3_round CODE_FOR_nothing
#define CODE_FOR_addv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_addv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_subv4sf3 = 4184,
#define CODE_FOR_subv4sf3_round CODE_FOR_nothing
#define CODE_FOR_subv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_subv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_addv8df3 = 4185,
  CODE_FOR_addv8df3_round = 4186,
  CODE_FOR_addv8df3_mask = 4187,
  CODE_FOR_addv8df3_mask_round = 4188,
  CODE_FOR_subv8df3 = 4189,
  CODE_FOR_subv8df3_round = 4190,
  CODE_FOR_subv8df3_mask = 4191,
  CODE_FOR_subv8df3_mask_round = 4192,
  CODE_FOR_addv4df3 = 4193,
#define CODE_FOR_addv4df3_round CODE_FOR_nothing
#define CODE_FOR_addv4df3_mask CODE_FOR_nothing
#define CODE_FOR_addv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_subv4df3 = 4194,
#define CODE_FOR_subv4df3_round CODE_FOR_nothing
#define CODE_FOR_subv4df3_mask CODE_FOR_nothing
#define CODE_FOR_subv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_addv2df3 = 4195,
#define CODE_FOR_addv2df3_round CODE_FOR_nothing
#define CODE_FOR_addv2df3_mask CODE_FOR_nothing
#define CODE_FOR_addv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_subv2df3 = 4196,
#define CODE_FOR_subv2df3_round CODE_FOR_nothing
#define CODE_FOR_subv2df3_mask CODE_FOR_nothing
#define CODE_FOR_subv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv16sf3 = 4197,
  CODE_FOR_mulv16sf3_round = 4198,
  CODE_FOR_mulv16sf3_mask = 4199,
  CODE_FOR_mulv16sf3_mask_round = 4200,
  CODE_FOR_mulv8sf3 = 4201,
#define CODE_FOR_mulv8sf3_round CODE_FOR_nothing
#define CODE_FOR_mulv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_mulv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv4sf3 = 4202,
#define CODE_FOR_mulv4sf3_round CODE_FOR_nothing
#define CODE_FOR_mulv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_mulv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv8df3 = 4203,
  CODE_FOR_mulv8df3_round = 4204,
  CODE_FOR_mulv8df3_mask = 4205,
  CODE_FOR_mulv8df3_mask_round = 4206,
  CODE_FOR_mulv4df3 = 4207,
#define CODE_FOR_mulv4df3_round CODE_FOR_nothing
#define CODE_FOR_mulv4df3_mask CODE_FOR_nothing
#define CODE_FOR_mulv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_mulv2df3 = 4208,
#define CODE_FOR_mulv2df3_round CODE_FOR_nothing
#define CODE_FOR_mulv2df3_mask CODE_FOR_nothing
#define CODE_FOR_mulv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_divv8df3 = 4209,
  CODE_FOR_divv4df3 = 4210,
  CODE_FOR_divv2df3 = 4211,
  CODE_FOR_divv16sf3 = 4212,
  CODE_FOR_divv8sf3 = 4213,
  CODE_FOR_divv4sf3 = 4214,
  CODE_FOR_sqrtv8df2 = 4215,
  CODE_FOR_sqrtv4df2 = 4216,
  CODE_FOR_sqrtv2df2 = 4217,
  CODE_FOR_sqrtv16sf2 = 4218,
  CODE_FOR_sqrtv8sf2 = 4219,
  CODE_FOR_sqrtv4sf2 = 4220,
  CODE_FOR_rsqrtv8sf2 = 4221,
  CODE_FOR_rsqrtv4sf2 = 4222,
  CODE_FOR_smaxv16sf3 = 4223,
  CODE_FOR_smaxv16sf3_round = 4224,
  CODE_FOR_smaxv16sf3_mask = 4225,
  CODE_FOR_smaxv16sf3_mask_round = 4226,
  CODE_FOR_sminv16sf3 = 4227,
  CODE_FOR_sminv16sf3_round = 4228,
  CODE_FOR_sminv16sf3_mask = 4229,
  CODE_FOR_sminv16sf3_mask_round = 4230,
  CODE_FOR_smaxv8sf3 = 4231,
#define CODE_FOR_smaxv8sf3_round CODE_FOR_nothing
#define CODE_FOR_smaxv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv8sf3 = 4232,
#define CODE_FOR_sminv8sf3_round CODE_FOR_nothing
#define CODE_FOR_sminv8sf3_mask CODE_FOR_nothing
#define CODE_FOR_sminv8sf3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv4sf3 = 4233,
#define CODE_FOR_smaxv4sf3_round CODE_FOR_nothing
#define CODE_FOR_smaxv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv4sf3 = 4234,
#define CODE_FOR_sminv4sf3_round CODE_FOR_nothing
#define CODE_FOR_sminv4sf3_mask CODE_FOR_nothing
#define CODE_FOR_sminv4sf3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv8df3 = 4235,
  CODE_FOR_smaxv8df3_round = 4236,
  CODE_FOR_smaxv8df3_mask = 4237,
  CODE_FOR_smaxv8df3_mask_round = 4238,
  CODE_FOR_sminv8df3 = 4239,
  CODE_FOR_sminv8df3_round = 4240,
  CODE_FOR_sminv8df3_mask = 4241,
  CODE_FOR_sminv8df3_mask_round = 4242,
  CODE_FOR_smaxv4df3 = 4243,
#define CODE_FOR_smaxv4df3_round CODE_FOR_nothing
#define CODE_FOR_smaxv4df3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv4df3 = 4244,
#define CODE_FOR_sminv4df3_round CODE_FOR_nothing
#define CODE_FOR_sminv4df3_mask CODE_FOR_nothing
#define CODE_FOR_sminv4df3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv2df3 = 4245,
#define CODE_FOR_smaxv2df3_round CODE_FOR_nothing
#define CODE_FOR_smaxv2df3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv2df3 = 4246,
#define CODE_FOR_sminv2df3_round CODE_FOR_nothing
#define CODE_FOR_sminv2df3_mask CODE_FOR_nothing
#define CODE_FOR_sminv2df3_mask_round CODE_FOR_nothing
  CODE_FOR_sse3_haddv2df3 = 4247,
  CODE_FOR_reduc_splus_v8df = 4248,
  CODE_FOR_reduc_splus_v4df = 4249,
  CODE_FOR_reduc_splus_v2df = 4250,
  CODE_FOR_reduc_splus_v16sf = 4251,
  CODE_FOR_reduc_splus_v8sf = 4252,
  CODE_FOR_reduc_splus_v4sf = 4253,
  CODE_FOR_reduc_smax_v32qi = 4254,
  CODE_FOR_reduc_smin_v32qi = 4255,
  CODE_FOR_reduc_smax_v16hi = 4256,
  CODE_FOR_reduc_smin_v16hi = 4257,
  CODE_FOR_reduc_smax_v8si = 4258,
  CODE_FOR_reduc_smin_v8si = 4259,
  CODE_FOR_reduc_smax_v4di = 4260,
  CODE_FOR_reduc_smin_v4di = 4261,
  CODE_FOR_reduc_smax_v8sf = 4262,
  CODE_FOR_reduc_smin_v8sf = 4263,
  CODE_FOR_reduc_smax_v4df = 4264,
  CODE_FOR_reduc_smin_v4df = 4265,
  CODE_FOR_reduc_smax_v4sf = 4266,
  CODE_FOR_reduc_smin_v4sf = 4267,
  CODE_FOR_reduc_smax_v16si = 4268,
  CODE_FOR_reduc_smin_v16si = 4269,
  CODE_FOR_reduc_smax_v8di = 4270,
  CODE_FOR_reduc_smin_v8di = 4271,
  CODE_FOR_reduc_smax_v16sf = 4272,
  CODE_FOR_reduc_smin_v16sf = 4273,
  CODE_FOR_reduc_smax_v8df = 4274,
  CODE_FOR_reduc_smin_v8df = 4275,
  CODE_FOR_reduc_umax_v16si = 4276,
  CODE_FOR_reduc_umin_v16si = 4277,
  CODE_FOR_reduc_umax_v8di = 4278,
  CODE_FOR_reduc_umin_v8di = 4279,
  CODE_FOR_reduc_umax_v32qi = 4280,
  CODE_FOR_reduc_umin_v32qi = 4281,
  CODE_FOR_reduc_umax_v16hi = 4282,
  CODE_FOR_reduc_umin_v16hi = 4283,
  CODE_FOR_reduc_umax_v8si = 4284,
  CODE_FOR_reduc_umin_v8si = 4285,
  CODE_FOR_reduc_umax_v4di = 4286,
  CODE_FOR_reduc_umin_v4di = 4287,
  CODE_FOR_reduc_umin_v8hi = 4288,
  CODE_FOR_vcondv64qiv16sf = 4289,
  CODE_FOR_vcondv32hiv16sf = 4290,
  CODE_FOR_vcondv16siv16sf = 4291,
  CODE_FOR_vcondv8div16sf = 4292,
  CODE_FOR_vcondv16sfv16sf = 4293,
  CODE_FOR_vcondv8dfv16sf = 4294,
  CODE_FOR_vcondv64qiv8df = 4295,
  CODE_FOR_vcondv32hiv8df = 4296,
  CODE_FOR_vcondv16siv8df = 4297,
  CODE_FOR_vcondv8div8df = 4298,
  CODE_FOR_vcondv16sfv8df = 4299,
  CODE_FOR_vcondv8dfv8df = 4300,
  CODE_FOR_vcondv32qiv8sf = 4301,
  CODE_FOR_vcondv32qiv4df = 4302,
  CODE_FOR_vcondv16hiv8sf = 4303,
  CODE_FOR_vcondv16hiv4df = 4304,
  CODE_FOR_vcondv8siv8sf = 4305,
  CODE_FOR_vcondv8siv4df = 4306,
  CODE_FOR_vcondv4div8sf = 4307,
  CODE_FOR_vcondv4div4df = 4308,
  CODE_FOR_vcondv8sfv8sf = 4309,
  CODE_FOR_vcondv8sfv4df = 4310,
  CODE_FOR_vcondv4dfv8sf = 4311,
  CODE_FOR_vcondv4dfv4df = 4312,
  CODE_FOR_vcondv16qiv4sf = 4313,
  CODE_FOR_vcondv16qiv2df = 4314,
  CODE_FOR_vcondv8hiv4sf = 4315,
  CODE_FOR_vcondv8hiv2df = 4316,
  CODE_FOR_vcondv4siv4sf = 4317,
  CODE_FOR_vcondv4siv2df = 4318,
  CODE_FOR_vcondv2div4sf = 4319,
  CODE_FOR_vcondv2div2df = 4320,
  CODE_FOR_vcondv4sfv4sf = 4321,
  CODE_FOR_vcondv4sfv2df = 4322,
  CODE_FOR_vcondv2dfv4sf = 4323,
  CODE_FOR_vcondv2dfv2df = 4324,
  CODE_FOR_andv8sf3 = 4325,
  CODE_FOR_iorv8sf3 = 4326,
  CODE_FOR_xorv8sf3 = 4327,
  CODE_FOR_andv4sf3 = 4328,
  CODE_FOR_iorv4sf3 = 4329,
  CODE_FOR_xorv4sf3 = 4330,
  CODE_FOR_andv4df3 = 4331,
  CODE_FOR_iorv4df3 = 4332,
  CODE_FOR_xorv4df3 = 4333,
  CODE_FOR_andv2df3 = 4334,
  CODE_FOR_iorv2df3 = 4335,
  CODE_FOR_xorv2df3 = 4336,
  CODE_FOR_andv16sf3 = 4337,
  CODE_FOR_xorv16sf3 = 4338,
  CODE_FOR_andv8df3 = 4339,
  CODE_FOR_xorv8df3 = 4340,
  CODE_FOR_copysignv16sf3 = 4341,
  CODE_FOR_copysignv8sf3 = 4342,
  CODE_FOR_copysignv4sf3 = 4343,
  CODE_FOR_copysignv8df3 = 4344,
  CODE_FOR_copysignv4df3 = 4345,
  CODE_FOR_copysignv2df3 = 4346,
  CODE_FOR_andtf3 = 4347,
  CODE_FOR_iortf3 = 4348,
  CODE_FOR_xortf3 = 4349,
  CODE_FOR_fmasf4 = 4350,
  CODE_FOR_fmadf4 = 4351,
  CODE_FOR_fmav4sf4 = 4352,
  CODE_FOR_fmav2df4 = 4353,
  CODE_FOR_fmav8sf4 = 4354,
  CODE_FOR_fmav4df4 = 4355,
  CODE_FOR_fmav16sf4 = 4356,
  CODE_FOR_fmav8df4 = 4357,
  CODE_FOR_fmssf4 = 4358,
  CODE_FOR_fmsdf4 = 4359,
  CODE_FOR_fmsv4sf4 = 4360,
  CODE_FOR_fmsv2df4 = 4361,
  CODE_FOR_fmsv8sf4 = 4362,
  CODE_FOR_fmsv4df4 = 4363,
  CODE_FOR_fmsv16sf4 = 4364,
  CODE_FOR_fmsv8df4 = 4365,
  CODE_FOR_fnmasf4 = 4366,
  CODE_FOR_fnmadf4 = 4367,
  CODE_FOR_fnmav4sf4 = 4368,
  CODE_FOR_fnmav2df4 = 4369,
  CODE_FOR_fnmav8sf4 = 4370,
  CODE_FOR_fnmav4df4 = 4371,
  CODE_FOR_fnmav16sf4 = 4372,
  CODE_FOR_fnmav8df4 = 4373,
  CODE_FOR_fnmssf4 = 4374,
  CODE_FOR_fnmsdf4 = 4375,
  CODE_FOR_fnmsv4sf4 = 4376,
  CODE_FOR_fnmsv2df4 = 4377,
  CODE_FOR_fnmsv8sf4 = 4378,
  CODE_FOR_fnmsv4df4 = 4379,
  CODE_FOR_fnmsv16sf4 = 4380,
  CODE_FOR_fnmsv8df4 = 4381,
  CODE_FOR_fma4i_fmadd_sf = 4382,
  CODE_FOR_fma4i_fmadd_df = 4383,
  CODE_FOR_fma4i_fmadd_v4sf = 4384,
  CODE_FOR_fma4i_fmadd_v2df = 4385,
  CODE_FOR_fma4i_fmadd_v8sf = 4386,
  CODE_FOR_fma4i_fmadd_v4df = 4387,
  CODE_FOR_fma4i_fmadd_v16sf = 4388,
  CODE_FOR_fma4i_fmadd_v8df = 4389,
  CODE_FOR_avx512f_fmadd_v16sf_maskz = 4390,
  CODE_FOR_avx512f_fmadd_v16sf_maskz_round = 4391,
  CODE_FOR_avx512f_fmadd_v8df_maskz = 4392,
  CODE_FOR_avx512f_fmadd_v8df_maskz_round = 4393,
  CODE_FOR_fmaddsub_v16sf = 4394,
  CODE_FOR_fmaddsub_v8sf = 4395,
  CODE_FOR_fmaddsub_v4sf = 4396,
  CODE_FOR_fmaddsub_v8df = 4397,
  CODE_FOR_fmaddsub_v4df = 4398,
  CODE_FOR_fmaddsub_v2df = 4399,
  CODE_FOR_avx512f_fmaddsub_v16sf_maskz = 4400,
  CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round = 4401,
  CODE_FOR_avx512f_fmaddsub_v8df_maskz = 4402,
  CODE_FOR_avx512f_fmaddsub_v8df_maskz_round = 4403,
  CODE_FOR_fmai_vmfmadd_v4sf = 4404,
  CODE_FOR_fmai_vmfmadd_v4sf_round = 4405,
  CODE_FOR_fmai_vmfmadd_v2df = 4406,
  CODE_FOR_fmai_vmfmadd_v2df_round = 4407,
  CODE_FOR_fma4i_vmfmadd_v4sf = 4408,
  CODE_FOR_fma4i_vmfmadd_v2df = 4409,
  CODE_FOR_floatunsv16siv16sf2 = 4410,
  CODE_FOR_floatunsv8siv8sf2 = 4411,
  CODE_FOR_floatunsv4siv4sf2 = 4412,
  CODE_FOR_fixuns_truncv16sfv16si2 = 4413,
  CODE_FOR_fixuns_truncv8sfv8si2 = 4414,
  CODE_FOR_fixuns_truncv4sfv4si2 = 4415,
  CODE_FOR_avx_cvtpd2dq256_2 = 4416,
  CODE_FOR_sse2_cvtpd2dq = 4417,
  CODE_FOR_avx_cvttpd2dq256_2 = 4418,
  CODE_FOR_sse2_cvttpd2dq = 4419,
  CODE_FOR_sse2_cvtpd2ps = 4420,
  CODE_FOR_vec_unpacks_hi_v4sf = 4421,
  CODE_FOR_vec_unpacks_hi_v8sf = 4422,
  CODE_FOR_vec_unpacks_hi_v16sf = 4423,
  CODE_FOR_vec_unpacks_lo_v4sf = 4424,
  CODE_FOR_vec_unpacks_lo_v8sf = 4425,
  CODE_FOR_vec_unpacks_float_hi_v32hi = 4426,
  CODE_FOR_vec_unpacks_float_hi_v16hi = 4427,
  CODE_FOR_vec_unpacks_float_hi_v8hi = 4428,
  CODE_FOR_vec_unpacks_float_lo_v32hi = 4429,
  CODE_FOR_vec_unpacks_float_lo_v16hi = 4430,
  CODE_FOR_vec_unpacks_float_lo_v8hi = 4431,
  CODE_FOR_vec_unpacku_float_hi_v32hi = 4432,
  CODE_FOR_vec_unpacku_float_hi_v16hi = 4433,
  CODE_FOR_vec_unpacku_float_hi_v8hi = 4434,
  CODE_FOR_vec_unpacku_float_lo_v32hi = 4435,
  CODE_FOR_vec_unpacku_float_lo_v16hi = 4436,
  CODE_FOR_vec_unpacku_float_lo_v8hi = 4437,
  CODE_FOR_vec_unpacks_float_hi_v4si = 4438,
  CODE_FOR_vec_unpacks_float_lo_v4si = 4439,
  CODE_FOR_vec_unpacks_float_hi_v8si = 4440,
  CODE_FOR_vec_unpacks_float_lo_v8si = 4441,
  CODE_FOR_vec_unpacks_float_hi_v16si = 4442,
  CODE_FOR_vec_unpacks_float_lo_v16si = 4443,
  CODE_FOR_vec_unpacku_float_hi_v4si = 4444,
  CODE_FOR_vec_unpacku_float_lo_v4si = 4445,
  CODE_FOR_vec_unpacku_float_hi_v8si = 4446,
  CODE_FOR_vec_unpacku_float_hi_v16si = 4447,
  CODE_FOR_vec_unpacku_float_lo_v8si = 4448,
  CODE_FOR_vec_unpacku_float_lo_v16si = 4449,
  CODE_FOR_vec_pack_trunc_v8df = 4450,
  CODE_FOR_vec_pack_trunc_v4df = 4451,
  CODE_FOR_vec_pack_trunc_v2df = 4452,
  CODE_FOR_vec_pack_sfix_trunc_v8df = 4453,
  CODE_FOR_vec_pack_sfix_trunc_v4df = 4454,
  CODE_FOR_vec_pack_sfix_trunc_v2df = 4455,
  CODE_FOR_vec_pack_ufix_trunc_v8df = 4456,
  CODE_FOR_vec_pack_ufix_trunc_v4df = 4457,
  CODE_FOR_vec_pack_ufix_trunc_v2df = 4458,
  CODE_FOR_vec_pack_sfix_v4df = 4459,
  CODE_FOR_vec_pack_sfix_v2df = 4460,
  CODE_FOR_sse_movhlps_exp = 4461,
  CODE_FOR_sse_movlhps_exp = 4462,
  CODE_FOR_vec_interleave_highv8sf = 4463,
  CODE_FOR_vec_interleave_lowv8sf = 4464,
  CODE_FOR_avx_shufps256 = 4465,
  CODE_FOR_sse_shufps = 4466,
  CODE_FOR_sse_loadhps_exp = 4467,
  CODE_FOR_sse_loadlps_exp = 4468,
  CODE_FOR_vec_initv16qi = 4469,
  CODE_FOR_vec_initv8hi = 4470,
  CODE_FOR_vec_initv4si = 4471,
  CODE_FOR_vec_initv2di = 4472,
  CODE_FOR_vec_initv4sf = 4473,
  CODE_FOR_vec_initv2df = 4474,
  CODE_FOR_vec_setv32qi = 4477,
  CODE_FOR_vec_setv16qi = 4478,
  CODE_FOR_vec_setv16hi = 4479,
  CODE_FOR_vec_setv8hi = 4480,
  CODE_FOR_vec_setv16si = 4481,
  CODE_FOR_vec_setv8si = 4482,
  CODE_FOR_vec_setv4si = 4483,
  CODE_FOR_vec_setv8di = 4484,
  CODE_FOR_vec_setv4di = 4485,
  CODE_FOR_vec_setv2di = 4486,
  CODE_FOR_vec_setv16sf = 4487,
  CODE_FOR_vec_setv8sf = 4488,
  CODE_FOR_vec_setv4sf = 4489,
  CODE_FOR_vec_setv8df = 4490,
  CODE_FOR_vec_setv4df = 4491,
  CODE_FOR_vec_setv2df = 4492,
  CODE_FOR_avx512f_vextractf32x4_mask = 4496,
  CODE_FOR_avx512f_vextracti32x4_mask = 4497,
  CODE_FOR_avx512f_vextractf64x4_mask = 4498,
  CODE_FOR_avx512f_vextracti64x4_mask = 4499,
  CODE_FOR_avx_vextractf128v32qi = 4502,
  CODE_FOR_avx_vextractf128v16hi = 4503,
  CODE_FOR_avx_vextractf128v8si = 4504,
  CODE_FOR_avx_vextractf128v4di = 4505,
  CODE_FOR_avx_vextractf128v8sf = 4506,
  CODE_FOR_avx_vextractf128v4df = 4507,
  CODE_FOR_vec_extractv32qi = 4518,
  CODE_FOR_vec_extractv16qi = 4519,
  CODE_FOR_vec_extractv16hi = 4520,
  CODE_FOR_vec_extractv8hi = 4521,
  CODE_FOR_vec_extractv16si = 4522,
  CODE_FOR_vec_extractv8si = 4523,
  CODE_FOR_vec_extractv4si = 4524,
  CODE_FOR_vec_extractv8di = 4525,
  CODE_FOR_vec_extractv4di = 4526,
  CODE_FOR_vec_extractv2di = 4527,
  CODE_FOR_vec_extractv16sf = 4528,
  CODE_FOR_vec_extractv8sf = 4529,
  CODE_FOR_vec_extractv4sf = 4530,
  CODE_FOR_vec_extractv8df = 4531,
  CODE_FOR_vec_extractv4df = 4532,
  CODE_FOR_vec_extractv2df = 4533,
  CODE_FOR_vec_interleave_highv4df = 4534,
  CODE_FOR_vec_interleave_highv2df = 4535,
  CODE_FOR_avx512f_movddup512 = 4536,
  CODE_FOR_avx512f_movddup512_mask = 4537,
  CODE_FOR_avx512f_unpcklpd512 = 4538,
  CODE_FOR_avx512f_unpcklpd512_mask = 4539,
  CODE_FOR_avx_movddup256 = 4540,
  CODE_FOR_avx_unpcklpd256 = 4541,
  CODE_FOR_vec_interleave_lowv4df = 4542,
  CODE_FOR_vec_interleave_lowv2df = 4543,
  CODE_FOR_avx512f_vternlogv16si_maskz = 4546,
  CODE_FOR_avx512f_vternlogv8di_maskz = 4547,
  CODE_FOR_avx512f_shufps512_mask = 4548,
  CODE_FOR_avx512f_fixupimmv16sf_maskz = 4549,
  CODE_FOR_avx512f_fixupimmv16sf_maskz_round = 4550,
  CODE_FOR_avx512f_fixupimmv8df_maskz = 4551,
  CODE_FOR_avx512f_fixupimmv8df_maskz_round = 4552,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz = 4553,
  CODE_FOR_avx512f_sfixupimmv4sf_maskz_round = 4554,
  CODE_FOR_avx512f_sfixupimmv2df_maskz = 4555,
  CODE_FOR_avx512f_sfixupimmv2df_maskz_round = 4556,
  CODE_FOR_avx512f_shufpd512_mask = 4557,
  CODE_FOR_avx_shufpd256 = 4558,
  CODE_FOR_sse2_shufpd = 4559,
  CODE_FOR_sse2_loadhpd_exp = 4562,
  CODE_FOR_sse2_loadlpd_exp = 4564,
  CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store = 4566,
  CODE_FOR_avx512f_truncatev16siv16qi2_mask_store = 4567,
  CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store = 4568,
  CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store = 4569,
  CODE_FOR_avx512f_truncatev16siv16hi2_mask_store = 4570,
  CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store = 4571,
  CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store = 4572,
  CODE_FOR_avx512f_truncatev8div8si2_mask_store = 4573,
  CODE_FOR_avx512f_us_truncatev8div8si2_mask_store = 4574,
  CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store = 4575,
  CODE_FOR_avx512f_truncatev8div8hi2_mask_store = 4576,
  CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store = 4577,
  CODE_FOR_negv32qi2 = 4578,
  CODE_FOR_negv16qi2 = 4579,
  CODE_FOR_negv16hi2 = 4580,
  CODE_FOR_negv8hi2 = 4581,
  CODE_FOR_negv16si2 = 4582,
  CODE_FOR_negv8si2 = 4583,
  CODE_FOR_negv4si2 = 4584,
  CODE_FOR_negv8di2 = 4585,
  CODE_FOR_negv4di2 = 4586,
  CODE_FOR_negv2di2 = 4587,
  CODE_FOR_addv32qi3 = 4588,
  CODE_FOR_subv32qi3 = 4589,
  CODE_FOR_addv16qi3 = 4590,
#define CODE_FOR_addv16qi3_mask CODE_FOR_nothing
  CODE_FOR_subv16qi3 = 4591,
#define CODE_FOR_subv16qi3_mask CODE_FOR_nothing
  CODE_FOR_addv16hi3 = 4592,
#define CODE_FOR_addv16hi3_mask CODE_FOR_nothing
  CODE_FOR_subv16hi3 = 4593,
#define CODE_FOR_subv16hi3_mask CODE_FOR_nothing
  CODE_FOR_addv8hi3 = 4594,
#define CODE_FOR_addv8hi3_mask CODE_FOR_nothing
  CODE_FOR_subv8hi3 = 4595,
#define CODE_FOR_subv8hi3_mask CODE_FOR_nothing
  CODE_FOR_addv16si3 = 4596,
  CODE_FOR_addv16si3_mask = 4597,
  CODE_FOR_subv16si3 = 4598,
  CODE_FOR_subv16si3_mask = 4599,
  CODE_FOR_addv8si3 = 4600,
#define CODE_FOR_addv8si3_mask CODE_FOR_nothing
  CODE_FOR_subv8si3 = 4601,
#define CODE_FOR_subv8si3_mask CODE_FOR_nothing
  CODE_FOR_addv4si3 = 4602,
#define CODE_FOR_addv4si3_mask CODE_FOR_nothing
  CODE_FOR_subv4si3 = 4603,
#define CODE_FOR_subv4si3_mask CODE_FOR_nothing
  CODE_FOR_addv8di3 = 4604,
  CODE_FOR_addv8di3_mask = 4605,
  CODE_FOR_subv8di3 = 4606,
  CODE_FOR_subv8di3_mask = 4607,
  CODE_FOR_addv4di3 = 4608,
#define CODE_FOR_addv4di3_mask CODE_FOR_nothing
  CODE_FOR_subv4di3 = 4609,
#define CODE_FOR_subv4di3_mask CODE_FOR_nothing
  CODE_FOR_addv2di3 = 4610,
#define CODE_FOR_addv2di3_mask CODE_FOR_nothing
  CODE_FOR_subv2di3 = 4611,
#define CODE_FOR_subv2di3_mask CODE_FOR_nothing
  CODE_FOR_avx2_ssaddv32qi3 = 4612,
  CODE_FOR_avx2_usaddv32qi3 = 4613,
  CODE_FOR_avx2_sssubv32qi3 = 4614,
  CODE_FOR_avx2_ussubv32qi3 = 4615,
  CODE_FOR_sse2_ssaddv16qi3 = 4616,
  CODE_FOR_sse2_usaddv16qi3 = 4617,
  CODE_FOR_sse2_sssubv16qi3 = 4618,
  CODE_FOR_sse2_ussubv16qi3 = 4619,
  CODE_FOR_avx2_ssaddv16hi3 = 4620,
  CODE_FOR_avx2_usaddv16hi3 = 4621,
  CODE_FOR_avx2_sssubv16hi3 = 4622,
  CODE_FOR_avx2_ussubv16hi3 = 4623,
  CODE_FOR_sse2_ssaddv8hi3 = 4624,
  CODE_FOR_sse2_usaddv8hi3 = 4625,
  CODE_FOR_sse2_sssubv8hi3 = 4626,
  CODE_FOR_sse2_ussubv8hi3 = 4627,
  CODE_FOR_mulv32qi3 = 4628,
  CODE_FOR_mulv16qi3 = 4629,
  CODE_FOR_mulv16hi3 = 4630,
  CODE_FOR_mulv8hi3 = 4631,
  CODE_FOR_smulv16hi3_highpart = 4632,
  CODE_FOR_umulv16hi3_highpart = 4633,
  CODE_FOR_smulv8hi3_highpart = 4634,
  CODE_FOR_umulv8hi3_highpart = 4635,
  CODE_FOR_vec_widen_umult_even_v16si = 4636,
  CODE_FOR_vec_widen_umult_even_v16si_mask = 4637,
  CODE_FOR_vec_widen_umult_even_v8si = 4638,
  CODE_FOR_vec_widen_umult_even_v4si = 4639,
  CODE_FOR_vec_widen_smult_even_v16si = 4640,
  CODE_FOR_vec_widen_smult_even_v16si_mask = 4641,
  CODE_FOR_vec_widen_smult_even_v8si = 4642,
  CODE_FOR_sse4_1_mulv2siv2di3 = 4643,
  CODE_FOR_avx2_pmaddwd = 4644,
  CODE_FOR_sse2_pmaddwd = 4645,
  CODE_FOR_mulv16si3 = 4646,
  CODE_FOR_mulv16si3_mask = 4647,
  CODE_FOR_mulv8si3 = 4648,
#define CODE_FOR_mulv8si3_mask CODE_FOR_nothing
  CODE_FOR_mulv4si3 = 4649,
#define CODE_FOR_mulv4si3_mask CODE_FOR_nothing
  CODE_FOR_mulv8di3 = 4650,
  CODE_FOR_mulv4di3 = 4651,
  CODE_FOR_mulv2di3 = 4652,
  CODE_FOR_vec_widen_smult_hi_v32qi = 4653,
  CODE_FOR_vec_widen_umult_hi_v32qi = 4654,
  CODE_FOR_vec_widen_smult_hi_v16qi = 4655,
  CODE_FOR_vec_widen_umult_hi_v16qi = 4656,
  CODE_FOR_vec_widen_smult_hi_v16hi = 4657,
  CODE_FOR_vec_widen_umult_hi_v16hi = 4658,
  CODE_FOR_vec_widen_smult_hi_v8hi = 4659,
  CODE_FOR_vec_widen_umult_hi_v8hi = 4660,
  CODE_FOR_vec_widen_smult_hi_v8si = 4661,
  CODE_FOR_vec_widen_umult_hi_v8si = 4662,
  CODE_FOR_vec_widen_smult_hi_v4si = 4663,
  CODE_FOR_vec_widen_umult_hi_v4si = 4664,
  CODE_FOR_vec_widen_smult_lo_v32qi = 4665,
  CODE_FOR_vec_widen_umult_lo_v32qi = 4666,
  CODE_FOR_vec_widen_smult_lo_v16qi = 4667,
  CODE_FOR_vec_widen_umult_lo_v16qi = 4668,
  CODE_FOR_vec_widen_smult_lo_v16hi = 4669,
  CODE_FOR_vec_widen_umult_lo_v16hi = 4670,
  CODE_FOR_vec_widen_smult_lo_v8hi = 4671,
  CODE_FOR_vec_widen_umult_lo_v8hi = 4672,
  CODE_FOR_vec_widen_smult_lo_v8si = 4673,
  CODE_FOR_vec_widen_umult_lo_v8si = 4674,
  CODE_FOR_vec_widen_smult_lo_v4si = 4675,
  CODE_FOR_vec_widen_umult_lo_v4si = 4676,
  CODE_FOR_vec_widen_smult_even_v4si = 4677,
  CODE_FOR_vec_widen_smult_odd_v16si = 4678,
  CODE_FOR_vec_widen_umult_odd_v16si = 4679,
  CODE_FOR_vec_widen_smult_odd_v8si = 4680,
  CODE_FOR_vec_widen_umult_odd_v8si = 4681,
  CODE_FOR_vec_widen_smult_odd_v4si = 4682,
  CODE_FOR_vec_widen_umult_odd_v4si = 4683,
  CODE_FOR_sdot_prodv16hi = 4684,
  CODE_FOR_sdot_prodv8hi = 4685,
  CODE_FOR_sdot_prodv4si = 4686,
  CODE_FOR_vec_shl_v16qi = 4687,
  CODE_FOR_vec_shl_v8hi = 4688,
  CODE_FOR_vec_shl_v4si = 4689,
  CODE_FOR_vec_shl_v2di = 4690,
  CODE_FOR_vec_shr_v16qi = 4691,
  CODE_FOR_vec_shr_v8hi = 4692,
  CODE_FOR_vec_shr_v4si = 4693,
  CODE_FOR_vec_shr_v2di = 4694,
  CODE_FOR_smaxv32qi3 = 4695,
  CODE_FOR_sminv32qi3 = 4696,
  CODE_FOR_umaxv32qi3 = 4697,
  CODE_FOR_uminv32qi3 = 4698,
  CODE_FOR_smaxv16hi3 = 4699,
#define CODE_FOR_smaxv16hi3_round CODE_FOR_nothing
#define CODE_FOR_smaxv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv16hi3 = 4700,
#define CODE_FOR_sminv16hi3_round CODE_FOR_nothing
#define CODE_FOR_sminv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_sminv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv16hi3 = 4701,
#define CODE_FOR_umaxv16hi3_round CODE_FOR_nothing
#define CODE_FOR_umaxv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_umaxv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv16hi3 = 4702,
#define CODE_FOR_uminv16hi3_round CODE_FOR_nothing
#define CODE_FOR_uminv16hi3_mask CODE_FOR_nothing
#define CODE_FOR_uminv16hi3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv8si3 = 4703,
#define CODE_FOR_smaxv8si3_round CODE_FOR_nothing
#define CODE_FOR_smaxv8si3_mask CODE_FOR_nothing
#define CODE_FOR_smaxv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv8si3 = 4704,
#define CODE_FOR_sminv8si3_round CODE_FOR_nothing
#define CODE_FOR_sminv8si3_mask CODE_FOR_nothing
#define CODE_FOR_sminv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv8si3 = 4705,
#define CODE_FOR_umaxv8si3_round CODE_FOR_nothing
#define CODE_FOR_umaxv8si3_mask CODE_FOR_nothing
#define CODE_FOR_umaxv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv8si3 = 4706,
#define CODE_FOR_uminv8si3_round CODE_FOR_nothing
#define CODE_FOR_uminv8si3_mask CODE_FOR_nothing
#define CODE_FOR_uminv8si3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv8di3 = 4707,
#define CODE_FOR_smaxv8di3_round CODE_FOR_nothing
  CODE_FOR_smaxv8di3_mask = 4708,
#define CODE_FOR_smaxv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv8di3 = 4709,
#define CODE_FOR_sminv8di3_round CODE_FOR_nothing
  CODE_FOR_sminv8di3_mask = 4710,
#define CODE_FOR_sminv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv8di3 = 4711,
#define CODE_FOR_umaxv8di3_round CODE_FOR_nothing
  CODE_FOR_umaxv8di3_mask = 4712,
#define CODE_FOR_umaxv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv8di3 = 4713,
#define CODE_FOR_uminv8di3_round CODE_FOR_nothing
  CODE_FOR_uminv8di3_mask = 4714,
#define CODE_FOR_uminv8di3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv16si3 = 4715,
#define CODE_FOR_smaxv16si3_round CODE_FOR_nothing
  CODE_FOR_smaxv16si3_mask = 4716,
#define CODE_FOR_smaxv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_sminv16si3 = 4717,
#define CODE_FOR_sminv16si3_round CODE_FOR_nothing
  CODE_FOR_sminv16si3_mask = 4718,
#define CODE_FOR_sminv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_umaxv16si3 = 4719,
#define CODE_FOR_umaxv16si3_round CODE_FOR_nothing
  CODE_FOR_umaxv16si3_mask = 4720,
#define CODE_FOR_umaxv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_uminv16si3 = 4721,
#define CODE_FOR_uminv16si3_round CODE_FOR_nothing
  CODE_FOR_uminv16si3_mask = 4722,
#define CODE_FOR_uminv16si3_mask_round CODE_FOR_nothing
  CODE_FOR_smaxv4di3 = 4723,
  CODE_FOR_sminv4di3 = 4724,
  CODE_FOR_umaxv4di3 = 4725,
  CODE_FOR_uminv4di3 = 4726,
  CODE_FOR_smaxv2di3 = 4727,
  CODE_FOR_sminv2di3 = 4728,
  CODE_FOR_umaxv2di3 = 4729,
  CODE_FOR_uminv2di3 = 4730,
  CODE_FOR_smaxv16qi3 = 4731,
  CODE_FOR_sminv16qi3 = 4732,
  CODE_FOR_smaxv8hi3 = 4733,
  CODE_FOR_sminv8hi3 = 4734,
  CODE_FOR_smaxv4si3 = 4735,
  CODE_FOR_sminv4si3 = 4736,
  CODE_FOR_umaxv16qi3 = 4737,
  CODE_FOR_uminv16qi3 = 4738,
  CODE_FOR_umaxv8hi3 = 4739,
  CODE_FOR_uminv8hi3 = 4740,
  CODE_FOR_umaxv4si3 = 4741,
  CODE_FOR_uminv4si3 = 4742,
  CODE_FOR_avx2_eqv32qi3 = 4743,
  CODE_FOR_avx2_eqv16hi3 = 4744,
  CODE_FOR_avx2_eqv8si3 = 4745,
  CODE_FOR_avx2_eqv4di3 = 4746,
  CODE_FOR_avx512f_eqv16si3 = 4747,
  CODE_FOR_avx512f_eqv16si3_mask = 4748,
  CODE_FOR_avx512f_eqv8di3 = 4749,
  CODE_FOR_avx512f_eqv8di3_mask = 4750,
  CODE_FOR_sse2_eqv16qi3 = 4751,
  CODE_FOR_sse2_eqv8hi3 = 4752,
  CODE_FOR_sse2_eqv4si3 = 4753,
  CODE_FOR_sse4_1_eqv2di3 = 4754,
  CODE_FOR_vcondv64qiv64qi = 4755,
  CODE_FOR_vcondv32hiv64qi = 4756,
  CODE_FOR_vcondv16siv64qi = 4757,
  CODE_FOR_vcondv8div64qi = 4758,
  CODE_FOR_vcondv16sfv64qi = 4759,
  CODE_FOR_vcondv8dfv64qi = 4760,
  CODE_FOR_vcondv64qiv32hi = 4761,
  CODE_FOR_vcondv32hiv32hi = 4762,
  CODE_FOR_vcondv16siv32hi = 4763,
  CODE_FOR_vcondv8div32hi = 4764,
  CODE_FOR_vcondv16sfv32hi = 4765,
  CODE_FOR_vcondv8dfv32hi = 4766,
  CODE_FOR_vcondv64qiv16si = 4767,
  CODE_FOR_vcondv32hiv16si = 4768,
  CODE_FOR_vcondv16siv16si = 4769,
  CODE_FOR_vcondv8div16si = 4770,
  CODE_FOR_vcondv16sfv16si = 4771,
  CODE_FOR_vcondv8dfv16si = 4772,
  CODE_FOR_vcondv64qiv8di = 4773,
  CODE_FOR_vcondv32hiv8di = 4774,
  CODE_FOR_vcondv16siv8di = 4775,
  CODE_FOR_vcondv8div8di = 4776,
  CODE_FOR_vcondv16sfv8di = 4777,
  CODE_FOR_vcondv8dfv8di = 4778,
  CODE_FOR_vcondv32qiv32qi = 4779,
  CODE_FOR_vcondv16hiv32qi = 4780,
  CODE_FOR_vcondv8siv32qi = 4781,
  CODE_FOR_vcondv4div32qi = 4782,
  CODE_FOR_vcondv8sfv32qi = 4783,
  CODE_FOR_vcondv4dfv32qi = 4784,
  CODE_FOR_vcondv32qiv16hi = 4785,
  CODE_FOR_vcondv16hiv16hi = 4786,
  CODE_FOR_vcondv8siv16hi = 4787,
  CODE_FOR_vcondv4div16hi = 4788,
  CODE_FOR_vcondv8sfv16hi = 4789,
  CODE_FOR_vcondv4dfv16hi = 4790,
  CODE_FOR_vcondv32qiv8si = 4791,
  CODE_FOR_vcondv16hiv8si = 4792,
  CODE_FOR_vcondv8siv8si = 4793,
  CODE_FOR_vcondv4div8si = 4794,
  CODE_FOR_vcondv8sfv8si = 4795,
  CODE_FOR_vcondv4dfv8si = 4796,
  CODE_FOR_vcondv32qiv4di = 4797,
  CODE_FOR_vcondv16hiv4di = 4798,
  CODE_FOR_vcondv8siv4di = 4799,
  CODE_FOR_vcondv4div4di = 4800,
  CODE_FOR_vcondv8sfv4di = 4801,
  CODE_FOR_vcondv4dfv4di = 4802,
  CODE_FOR_vcondv16qiv16qi = 4803,
  CODE_FOR_vcondv16qiv8hi = 4804,
  CODE_FOR_vcondv16qiv4si = 4805,
  CODE_FOR_vcondv8hiv16qi = 4806,
  CODE_FOR_vcondv8hiv8hi = 4807,
  CODE_FOR_vcondv8hiv4si = 4808,
  CODE_FOR_vcondv4siv16qi = 4809,
  CODE_FOR_vcondv4siv8hi = 4810,
  CODE_FOR_vcondv4siv4si = 4811,
  CODE_FOR_vcondv2div16qi = 4812,
  CODE_FOR_vcondv2div8hi = 4813,
  CODE_FOR_vcondv2div4si = 4814,
  CODE_FOR_vcondv4sfv16qi = 4815,
  CODE_FOR_vcondv4sfv8hi = 4816,
  CODE_FOR_vcondv4sfv4si = 4817,
  CODE_FOR_vcondv2dfv16qi = 4818,
  CODE_FOR_vcondv2dfv8hi = 4819,
  CODE_FOR_vcondv2dfv4si = 4820,
  CODE_FOR_vcondv2div2di = 4821,
  CODE_FOR_vcondv2dfv2di = 4822,
  CODE_FOR_vconduv64qiv64qi = 4823,
  CODE_FOR_vconduv32hiv64qi = 4824,
  CODE_FOR_vconduv16siv64qi = 4825,
  CODE_FOR_vconduv8div64qi = 4826,
  CODE_FOR_vconduv16sfv64qi = 4827,
  CODE_FOR_vconduv8dfv64qi = 4828,
  CODE_FOR_vconduv64qiv32hi = 4829,
  CODE_FOR_vconduv32hiv32hi = 4830,
  CODE_FOR_vconduv16siv32hi = 4831,
  CODE_FOR_vconduv8div32hi = 4832,
  CODE_FOR_vconduv16sfv32hi = 4833,
  CODE_FOR_vconduv8dfv32hi = 4834,
  CODE_FOR_vconduv64qiv16si = 4835,
  CODE_FOR_vconduv32hiv16si = 4836,
  CODE_FOR_vconduv16siv16si = 4837,
  CODE_FOR_vconduv8div16si = 4838,
  CODE_FOR_vconduv16sfv16si = 4839,
  CODE_FOR_vconduv8dfv16si = 4840,
  CODE_FOR_vconduv64qiv8di = 4841,
  CODE_FOR_vconduv32hiv8di = 4842,
  CODE_FOR_vconduv16siv8di = 4843,
  CODE_FOR_vconduv8div8di = 4844,
  CODE_FOR_vconduv16sfv8di = 4845,
  CODE_FOR_vconduv8dfv8di = 4846,
  CODE_FOR_vconduv32qiv32qi = 4847,
  CODE_FOR_vconduv16hiv32qi = 4848,
  CODE_FOR_vconduv8siv32qi = 4849,
  CODE_FOR_vconduv4div32qi = 4850,
  CODE_FOR_vconduv8sfv32qi = 4851,
  CODE_FOR_vconduv4dfv32qi = 4852,
  CODE_FOR_vconduv32qiv16hi = 4853,
  CODE_FOR_vconduv16hiv16hi = 4854,
  CODE_FOR_vconduv8siv16hi = 4855,
  CODE_FOR_vconduv4div16hi = 4856,
  CODE_FOR_vconduv8sfv16hi = 4857,
  CODE_FOR_vconduv4dfv16hi = 4858,
  CODE_FOR_vconduv32qiv8si = 4859,
  CODE_FOR_vconduv16hiv8si = 4860,
  CODE_FOR_vconduv8siv8si = 4861,
  CODE_FOR_vconduv4div8si = 4862,
  CODE_FOR_vconduv8sfv8si = 4863,
  CODE_FOR_vconduv4dfv8si = 4864,
  CODE_FOR_vconduv32qiv4di = 4865,
  CODE_FOR_vconduv16hiv4di = 4866,
  CODE_FOR_vconduv8siv4di = 4867,
  CODE_FOR_vconduv4div4di = 4868,
  CODE_FOR_vconduv8sfv4di = 4869,
  CODE_FOR_vconduv4dfv4di = 4870,
  CODE_FOR_vconduv16qiv16qi = 4871,
  CODE_FOR_vconduv16qiv8hi = 4872,
  CODE_FOR_vconduv16qiv4si = 4873,
  CODE_FOR_vconduv8hiv16qi = 4874,
  CODE_FOR_vconduv8hiv8hi = 4875,
  CODE_FOR_vconduv8hiv4si = 4876,
  CODE_FOR_vconduv4siv16qi = 4877,
  CODE_FOR_vconduv4siv8hi = 4878,
  CODE_FOR_vconduv4siv4si = 4879,
  CODE_FOR_vconduv2div16qi = 4880,
  CODE_FOR_vconduv2div8hi = 4881,
  CODE_FOR_vconduv2div4si = 4882,
  CODE_FOR_vconduv4sfv16qi = 4883,
  CODE_FOR_vconduv4sfv8hi = 4884,
  CODE_FOR_vconduv4sfv4si = 4885,
  CODE_FOR_vconduv2dfv16qi = 4886,
  CODE_FOR_vconduv2dfv8hi = 4887,
  CODE_FOR_vconduv2dfv4si = 4888,
  CODE_FOR_vconduv2div2di = 4889,
  CODE_FOR_vconduv2dfv2di = 4890,
  CODE_FOR_vec_permv16qi = 4891,
  CODE_FOR_vec_permv8hi = 4892,
  CODE_FOR_vec_permv4si = 4893,
  CODE_FOR_vec_permv2di = 4894,
  CODE_FOR_vec_permv4sf = 4895,
  CODE_FOR_vec_permv2df = 4896,
  CODE_FOR_vec_permv32qi = 4897,
  CODE_FOR_vec_permv16hi = 4898,
  CODE_FOR_vec_permv8si = 4899,
  CODE_FOR_vec_permv4di = 4900,
  CODE_FOR_vec_permv8sf = 4901,
  CODE_FOR_vec_permv4df = 4902,
  CODE_FOR_vec_permv16sf = 4903,
  CODE_FOR_vec_permv8df = 4904,
  CODE_FOR_vec_permv16si = 4905,
  CODE_FOR_vec_permv8di = 4906,
  CODE_FOR_vec_perm_constv4sf = 4907,
  CODE_FOR_vec_perm_constv4si = 4908,
  CODE_FOR_vec_perm_constv2df = 4909,
  CODE_FOR_vec_perm_constv2di = 4910,
  CODE_FOR_vec_perm_constv16qi = 4911,
  CODE_FOR_vec_perm_constv8hi = 4912,
  CODE_FOR_vec_perm_constv8sf = 4913,
  CODE_FOR_vec_perm_constv4df = 4914,
  CODE_FOR_vec_perm_constv8si = 4915,
  CODE_FOR_vec_perm_constv4di = 4916,
  CODE_FOR_vec_perm_constv32qi = 4917,
  CODE_FOR_vec_perm_constv16hi = 4918,
  CODE_FOR_vec_perm_constv16si = 4919,
  CODE_FOR_vec_perm_constv8di = 4920,
  CODE_FOR_vec_perm_constv16sf = 4921,
  CODE_FOR_vec_perm_constv8df = 4922,
  CODE_FOR_one_cmplv16si2 = 4923,
  CODE_FOR_one_cmplv8di2 = 4924,
  CODE_FOR_one_cmplv32qi2 = 4925,
  CODE_FOR_one_cmplv16qi2 = 4926,
  CODE_FOR_one_cmplv16hi2 = 4927,
  CODE_FOR_one_cmplv8hi2 = 4928,
  CODE_FOR_one_cmplv8si2 = 4929,
  CODE_FOR_one_cmplv4si2 = 4930,
  CODE_FOR_one_cmplv4di2 = 4931,
  CODE_FOR_one_cmplv2di2 = 4932,
  CODE_FOR_avx2_andnotv32qi3 = 4933,
  CODE_FOR_sse2_andnotv16qi3 = 4934,
#define CODE_FOR_sse2_andnotv16qi3_mask CODE_FOR_nothing
  CODE_FOR_avx2_andnotv16hi3 = 4935,
#define CODE_FOR_avx2_andnotv16hi3_mask CODE_FOR_nothing
  CODE_FOR_sse2_andnotv8hi3 = 4936,
#define CODE_FOR_sse2_andnotv8hi3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_andnotv16si3 = 4937,
  CODE_FOR_avx512f_andnotv16si3_mask = 4938,
  CODE_FOR_avx2_andnotv8si3 = 4939,
#define CODE_FOR_avx2_andnotv8si3_mask CODE_FOR_nothing
  CODE_FOR_sse2_andnotv4si3 = 4940,
#define CODE_FOR_sse2_andnotv4si3_mask CODE_FOR_nothing
  CODE_FOR_avx512f_andnotv8di3 = 4941,
  CODE_FOR_avx512f_andnotv8di3_mask = 4942,
  CODE_FOR_avx2_andnotv4di3 = 4943,
#define CODE_FOR_avx2_andnotv4di3_mask CODE_FOR_nothing
  CODE_FOR_sse2_andnotv2di3 = 4944,
#define CODE_FOR_sse2_andnotv2di3_mask CODE_FOR_nothing
  CODE_FOR_andv16si3 = 4945,
  CODE_FOR_iorv16si3 = 4946,
  CODE_FOR_xorv16si3 = 4947,
  CODE_FOR_andv8di3 = 4948,
  CODE_FOR_iorv8di3 = 4949,
  CODE_FOR_xorv8di3 = 4950,
  CODE_FOR_andv32qi3 = 4951,
  CODE_FOR_iorv32qi3 = 4952,
  CODE_FOR_xorv32qi3 = 4953,
  CODE_FOR_andv16qi3 = 4954,
  CODE_FOR_iorv16qi3 = 4955,
  CODE_FOR_xorv16qi3 = 4956,
  CODE_FOR_andv16hi3 = 4957,
  CODE_FOR_iorv16hi3 = 4958,
  CODE_FOR_xorv16hi3 = 4959,
  CODE_FOR_andv8hi3 = 4960,
  CODE_FOR_iorv8hi3 = 4961,
  CODE_FOR_xorv8hi3 = 4962,
  CODE_FOR_andv8si3 = 4963,
  CODE_FOR_iorv8si3 = 4964,
  CODE_FOR_xorv8si3 = 4965,
  CODE_FOR_andv4si3 = 4966,
  CODE_FOR_iorv4si3 = 4967,
  CODE_FOR_xorv4si3 = 4968,
  CODE_FOR_andv4di3 = 4969,
  CODE_FOR_iorv4di3 = 4970,
  CODE_FOR_xorv4di3 = 4971,
  CODE_FOR_andv2di3 = 4972,
  CODE_FOR_iorv2di3 = 4973,
  CODE_FOR_xorv2di3 = 4974,
  CODE_FOR_vec_pack_trunc_v16hi = 4975,
  CODE_FOR_vec_pack_trunc_v8hi = 4976,
  CODE_FOR_vec_pack_trunc_v8si = 4977,
  CODE_FOR_vec_pack_trunc_v4si = 4978,
  CODE_FOR_vec_pack_trunc_v8di = 4979,
  CODE_FOR_vec_pack_trunc_v4di = 4980,
  CODE_FOR_vec_pack_trunc_v2di = 4981,
  CODE_FOR_vec_interleave_highv32qi = 4982,
  CODE_FOR_vec_interleave_highv16hi = 4983,
  CODE_FOR_vec_interleave_highv8si = 4984,
  CODE_FOR_vec_interleave_highv4di = 4985,
  CODE_FOR_vec_interleave_lowv32qi = 4986,
  CODE_FOR_vec_interleave_lowv16hi = 4987,
  CODE_FOR_vec_interleave_lowv8si = 4988,
  CODE_FOR_vec_interleave_lowv4di = 4989,
  CODE_FOR_avx512f_vinsertf32x4_mask = 4990,
  CODE_FOR_avx512f_vinserti32x4_mask = 4991,
  CODE_FOR_avx512f_vinsertf64x4_mask = 4992,
  CODE_FOR_avx512f_vinserti64x4_mask = 4993,
  CODE_FOR_avx512f_shuf_f64x2_mask = 4994,
  CODE_FOR_avx512f_shuf_i64x2_mask = 4995,
  CODE_FOR_avx512f_shuf_f32x4_mask = 4996,
  CODE_FOR_avx512f_shuf_i32x4_mask = 4997,
  CODE_FOR_avx512f_pshufdv3_mask = 4998,
  CODE_FOR_avx2_pshufdv3 = 4999,
  CODE_FOR_sse2_pshufd = 5000,
  CODE_FOR_avx2_pshuflwv3 = 5001,
  CODE_FOR_sse2_pshuflw = 5002,
  CODE_FOR_avx2_pshufhwv3 = 5003,
  CODE_FOR_sse2_pshufhw = 5004,
  CODE_FOR_sse2_loadd = 5005,
  CODE_FOR_vec_unpacks_lo_v32qi = 5014,
  CODE_FOR_vec_unpacks_lo_v16qi = 5015,
  CODE_FOR_vec_unpacks_lo_v32hi = 5016,
  CODE_FOR_vec_unpacks_lo_v16hi = 5017,
  CODE_FOR_vec_unpacks_lo_v8hi = 5018,
  CODE_FOR_vec_unpacks_lo_v16si = 5019,
  CODE_FOR_vec_unpacks_lo_v8si = 5020,
  CODE_FOR_vec_unpacks_lo_v4si = 5021,
  CODE_FOR_vec_unpacks_hi_v32qi = 5022,
  CODE_FOR_vec_unpacks_hi_v16qi = 5023,
  CODE_FOR_vec_unpacks_hi_v32hi = 5024,
  CODE_FOR_vec_unpacks_hi_v16hi = 5025,
  CODE_FOR_vec_unpacks_hi_v8hi = 5026,
  CODE_FOR_vec_unpacks_hi_v16si = 5027,
  CODE_FOR_vec_unpacks_hi_v8si = 5028,
  CODE_FOR_vec_unpacks_hi_v4si = 5029,
  CODE_FOR_vec_unpacku_lo_v32qi = 5030,
  CODE_FOR_vec_unpacku_lo_v16qi = 5031,
  CODE_FOR_vec_unpacku_lo_v32hi = 5032,
  CODE_FOR_vec_unpacku_lo_v16hi = 5033,
  CODE_FOR_vec_unpacku_lo_v8hi = 5034,
  CODE_FOR_vec_unpacku_lo_v16si = 5035,
  CODE_FOR_vec_unpacku_lo_v8si = 5036,
  CODE_FOR_vec_unpacku_lo_v4si = 5037,
  CODE_FOR_vec_unpacku_hi_v32qi = 5038,
  CODE_FOR_vec_unpacku_hi_v16qi = 5039,
  CODE_FOR_vec_unpacku_hi_v32hi = 5040,
  CODE_FOR_vec_unpacku_hi_v16hi = 5041,
  CODE_FOR_vec_unpacku_hi_v8hi = 5042,
  CODE_FOR_vec_unpacku_hi_v16si = 5043,
  CODE_FOR_vec_unpacku_hi_v8si = 5044,
  CODE_FOR_vec_unpacku_hi_v4si = 5045,
  CODE_FOR_avx2_uavgv32qi3 = 5046,
  CODE_FOR_sse2_uavgv16qi3 = 5047,
  CODE_FOR_avx2_uavgv16hi3 = 5048,
  CODE_FOR_sse2_uavgv8hi3 = 5049,
  CODE_FOR_sse2_maskmovdqu = 5050,
  CODE_FOR_ssse3_pmulhrswv4hi3 = 5051,
  CODE_FOR_ssse3_pmulhrswv8hi3 = 5052,
  CODE_FOR_avx2_pmulhrswv16hi3 = 5053,
  CODE_FOR_absv32qi2 = 5054,
  CODE_FOR_absv16qi2 = 5055,
  CODE_FOR_absv16hi2 = 5056,
  CODE_FOR_absv8hi2 = 5057,
  CODE_FOR_absv16si2 = 5058,
  CODE_FOR_absv8si2 = 5059,
  CODE_FOR_absv4si2 = 5060,
  CODE_FOR_absv8di2 = 5061,
  CODE_FOR_avx2_pblendw = 5062,
  CODE_FOR_avx_roundps_sfix256 = 5063,
  CODE_FOR_sse4_1_roundps_sfix = 5064,
  CODE_FOR_avx512f_roundpd512 = 5065,
  CODE_FOR_avx512f_roundpd_vec_pack_sfix512 = 5066,
  CODE_FOR_avx_roundpd_vec_pack_sfix256 = 5067,
  CODE_FOR_sse4_1_roundpd_vec_pack_sfix = 5068,
  CODE_FOR_roundv16sf2 = 5069,
  CODE_FOR_roundv8sf2 = 5070,
  CODE_FOR_roundv4sf2 = 5071,
  CODE_FOR_roundv8df2 = 5072,
  CODE_FOR_roundv4df2 = 5073,
  CODE_FOR_roundv2df2 = 5074,
  CODE_FOR_roundv8sf2_sfix = 5075,
  CODE_FOR_roundv4sf2_sfix = 5076,
  CODE_FOR_roundv8df2_vec_pack_sfix = 5077,
  CODE_FOR_roundv4df2_vec_pack_sfix = 5078,
  CODE_FOR_roundv2df2_vec_pack_sfix = 5079,
  CODE_FOR_avx512pf_gatherpfv16sisf = 5084,
  CODE_FOR_avx512pf_gatherpfv8disf = 5085,
  CODE_FOR_avx512pf_gatherpfv8sidf = 5086,
  CODE_FOR_avx512pf_gatherpfv8didf = 5087,
  CODE_FOR_avx512pf_scatterpfv16sisf = 5088,
  CODE_FOR_avx512pf_scatterpfv8disf = 5089,
  CODE_FOR_avx512pf_scatterpfv8sidf = 5090,
  CODE_FOR_avx512pf_scatterpfv8didf = 5091,
  CODE_FOR_rotlv16qi3 = 5092,
  CODE_FOR_rotlv8hi3 = 5093,
  CODE_FOR_rotlv4si3 = 5094,
  CODE_FOR_rotlv2di3 = 5095,
  CODE_FOR_rotrv16qi3 = 5096,
  CODE_FOR_rotrv8hi3 = 5097,
  CODE_FOR_rotrv4si3 = 5098,
  CODE_FOR_rotrv2di3 = 5099,
  CODE_FOR_vrotrv16qi3 = 5100,
  CODE_FOR_vrotrv8hi3 = 5101,
  CODE_FOR_vrotrv4si3 = 5102,
  CODE_FOR_vrotrv2di3 = 5103,
  CODE_FOR_vrotlv16qi3 = 5104,
  CODE_FOR_vrotlv8hi3 = 5105,
  CODE_FOR_vrotlv4si3 = 5106,
  CODE_FOR_vrotlv2di3 = 5107,
  CODE_FOR_vlshrv16qi3 = 5108,
  CODE_FOR_vlshrv8hi3 = 5109,
  CODE_FOR_vlshrv4si3 = 5110,
  CODE_FOR_vlshrv2di3 = 5111,
  CODE_FOR_vlshrv16si3 = 5112,
  CODE_FOR_vlshrv8di3 = 5113,
  CODE_FOR_vlshrv8si3 = 5114,
  CODE_FOR_vlshrv4di3 = 5115,
  CODE_FOR_vashrv16qi3 = 5116,
  CODE_FOR_vashrv8hi3 = 5117,
  CODE_FOR_vashrv2di3 = 5118,
  CODE_FOR_vashrv4si3 = 5119,
  CODE_FOR_vashrv16si3 = 5120,
  CODE_FOR_vashrv8si3 = 5121,
  CODE_FOR_vashlv16qi3 = 5122,
  CODE_FOR_vashlv8hi3 = 5123,
  CODE_FOR_vashlv4si3 = 5124,
  CODE_FOR_vashlv2di3 = 5125,
  CODE_FOR_vashlv16si3 = 5126,
  CODE_FOR_vashlv8di3 = 5127,
  CODE_FOR_vashlv8si3 = 5128,
  CODE_FOR_vashlv4di3 = 5129,
  CODE_FOR_ashlv32qi3 = 5130,
  CODE_FOR_lshrv32qi3 = 5131,
  CODE_FOR_ashrv32qi3 = 5132,
  CODE_FOR_ashlv16qi3 = 5133,
  CODE_FOR_lshrv16qi3 = 5134,
  CODE_FOR_ashrv16qi3 = 5135,
  CODE_FOR_ashrv2di3 = 5136,
  CODE_FOR_xop_vmfrczv4sf2 = 5137,
  CODE_FOR_xop_vmfrczv2df2 = 5138,
  CODE_FOR_avx_vzeroall = 5139,
  CODE_FOR_avx2_permv4di = 5140,
  CODE_FOR_avx2_permv4df = 5141,
  CODE_FOR_avx512f_permv8di = 5142,
  CODE_FOR_avx512f_permv8df = 5143,
  CODE_FOR_avx512f_permv8df_mask = 5144,
  CODE_FOR_avx512f_permv8di_mask = 5145,
  CODE_FOR_avx512f_vpermilv8df = 5152,
  CODE_FOR_avx512f_vpermilv8df_mask = 5153,
  CODE_FOR_avx_vpermilv4df = 5154,
#define CODE_FOR_avx_vpermilv4df_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilv2df = 5155,
#define CODE_FOR_avx_vpermilv2df_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermilv16sf = 5156,
  CODE_FOR_avx512f_vpermilv16sf_mask = 5157,
  CODE_FOR_avx_vpermilv8sf = 5158,
#define CODE_FOR_avx_vpermilv8sf_mask CODE_FOR_nothing
  CODE_FOR_avx_vpermilv4sf = 5159,
#define CODE_FOR_avx_vpermilv4sf_mask CODE_FOR_nothing
  CODE_FOR_avx512f_vpermi2varv16si3_maskz = 5160,
  CODE_FOR_avx512f_vpermi2varv16sf3_maskz = 5161,
  CODE_FOR_avx512f_vpermi2varv8di3_maskz = 5162,
  CODE_FOR_avx512f_vpermi2varv8df3_maskz = 5163,
  CODE_FOR_avx512f_vpermt2varv16si3_maskz = 5164,
  CODE_FOR_avx512f_vpermt2varv16sf3_maskz = 5165,
  CODE_FOR_avx512f_vpermt2varv8di3_maskz = 5166,
  CODE_FOR_avx512f_vpermt2varv8df3_maskz = 5167,
  CODE_FOR_avx_vperm2f128v8si3 = 5168,
  CODE_FOR_avx_vperm2f128v8sf3 = 5169,
  CODE_FOR_avx_vperm2f128v4df3 = 5170,
  CODE_FOR_avx_vinsertf128v32qi = 5171,
  CODE_FOR_avx_vinsertf128v16hi = 5172,
  CODE_FOR_avx_vinsertf128v8si = 5173,
  CODE_FOR_avx_vinsertf128v4di = 5174,
  CODE_FOR_avx_vinsertf128v8sf = 5175,
  CODE_FOR_avx_vinsertf128v4df = 5176,
  CODE_FOR_maskloadv4sf = 5177,
  CODE_FOR_maskloadv2df = 5178,
  CODE_FOR_maskloadv8sf = 5179,
  CODE_FOR_maskloadv4df = 5180,
  CODE_FOR_maskloadv4si = 5181,
  CODE_FOR_maskloadv2di = 5182,
  CODE_FOR_maskloadv8si = 5183,
  CODE_FOR_maskloadv4di = 5184,
  CODE_FOR_maskstorev4sf = 5185,
  CODE_FOR_maskstorev2df = 5186,
  CODE_FOR_maskstorev8sf = 5187,
  CODE_FOR_maskstorev4df = 5188,
  CODE_FOR_maskstorev4si = 5189,
  CODE_FOR_maskstorev2di = 5190,
  CODE_FOR_maskstorev8si = 5191,
  CODE_FOR_maskstorev4di = 5192,
  CODE_FOR_vec_initv32qi = 5196,
  CODE_FOR_vec_initv16hi = 5197,
  CODE_FOR_vec_initv8si = 5198,
  CODE_FOR_vec_initv4di = 5199,
  CODE_FOR_vec_initv8sf = 5200,
  CODE_FOR_vec_initv4df = 5201,
  CODE_FOR_vec_initv16si = 5202,
  CODE_FOR_vec_initv16sf = 5203,
  CODE_FOR_vec_initv8di = 5204,
  CODE_FOR_vec_initv8df = 5205,
  CODE_FOR_avx2_extracti128 = 5206,
  CODE_FOR_avx2_inserti128 = 5207,
  CODE_FOR_vcvtps2ph = 5208,
  CODE_FOR_avx2_gathersiv2di = 5209,
  CODE_FOR_avx2_gathersiv2df = 5210,
  CODE_FOR_avx2_gathersiv4di = 5211,
  CODE_FOR_avx2_gathersiv4df = 5212,
  CODE_FOR_avx2_gathersiv4si = 5213,
  CODE_FOR_avx2_gathersiv4sf = 5214,
  CODE_FOR_avx2_gathersiv8si = 5215,
  CODE_FOR_avx2_gathersiv8sf = 5216,
  CODE_FOR_avx2_gatherdiv2di = 5217,
  CODE_FOR_avx2_gatherdiv2df = 5218,
  CODE_FOR_avx2_gatherdiv4di = 5219,
  CODE_FOR_avx2_gatherdiv4df = 5220,
  CODE_FOR_avx2_gatherdiv4si = 5221,
  CODE_FOR_avx2_gatherdiv4sf = 5222,
  CODE_FOR_avx2_gatherdiv8si = 5223,
  CODE_FOR_avx2_gatherdiv8sf = 5224,
  CODE_FOR_avx512f_gathersiv16si = 5225,
  CODE_FOR_avx512f_gathersiv16sf = 5226,
  CODE_FOR_avx512f_gathersiv8di = 5227,
  CODE_FOR_avx512f_gathersiv8df = 5228,
  CODE_FOR_avx512f_gatherdiv16si = 5229,
  CODE_FOR_avx512f_gatherdiv16sf = 5230,
  CODE_FOR_avx512f_gatherdiv8di = 5231,
  CODE_FOR_avx512f_gatherdiv8df = 5232,
  CODE_FOR_avx512f_scattersiv16si = 5233,
  CODE_FOR_avx512f_scattersiv16sf = 5234,
  CODE_FOR_avx512f_scattersiv8di = 5235,
  CODE_FOR_avx512f_scattersiv8df = 5236,
  CODE_FOR_avx512f_scatterdiv16si = 5237,
  CODE_FOR_avx512f_scatterdiv16sf = 5238,
  CODE_FOR_avx512f_scatterdiv8di = 5239,
  CODE_FOR_avx512f_scatterdiv8df = 5240,
  CODE_FOR_avx512f_expandv16si_maskz = 5241,
  CODE_FOR_avx512f_expandv16sf_maskz = 5242,
  CODE_FOR_avx512f_expandv8di_maskz = 5243,
  CODE_FOR_avx512f_expandv8df_maskz = 5244,
  CODE_FOR_sse2_lfence = 5245,
  CODE_FOR_sse_sfence = 5246,
  CODE_FOR_sse2_mfence = 5247,
  CODE_FOR_mem_thread_fence = 5248,
  CODE_FOR_atomic_loadqi = 5249,
  CODE_FOR_atomic_loadhi = 5250,
  CODE_FOR_atomic_loadsi = 5251,
  CODE_FOR_atomic_loaddi = 5252,
  CODE_FOR_atomic_storeqi = 5254,
  CODE_FOR_atomic_storehi = 5255,
  CODE_FOR_atomic_storesi = 5256,
  CODE_FOR_atomic_storedi = 5257,
  CODE_FOR_atomic_compare_and_swapqi = 5259,
  CODE_FOR_atomic_compare_and_swaphi = 5260,
  CODE_FOR_atomic_compare_and_swapsi = 5261,
  CODE_FOR_atomic_compare_and_swapdi = 5262,
  CODE_FOR_atomic_compare_and_swapti = 5263,
  LAST_INSN_CODE
};

#endif /* GCC_INSN_CODES_H */
