46 unsigned int i = s2->
inputs();
65 s1->width() + hgap + s2->width(),
66 max(s1->height(), s2->height()) ),
165 for (
int i=0; i<N; i++) {
175 default : mx = 0; dx = 0;
break;
182 if (src.
y == dst.
y) {
187 dev.
trait(src.
x, src.
y, src.
x+mx, src.
y);
188 dev.
trait(src.
x+mx, src.
y, src.
x+mx, dst.
y);
189 dev.
trait(src.
x+mx, dst.
y, dst.
x, dst.
y);
195 for (
int i=0; i<N; i++) {
205 default : mx = 0; dx = 0;
break;
212 if (src.
y == dst.
y) {
217 dev.
trait(src.
x, src.
y, src.
x+mx, src.
y);
218 dev.
trait(src.
x+mx, src.
y, src.
x+mx, dst.
y);
219 dev.
trait(src.
x+mx, dst.
y, dst.
x, dst.
y);
244 for (
int i=0; i<N; i++) {
254 default : mx = 0; dx = 0;
break;
261 if (src.
y == dst.
y) {
274 for (
int i=0; i<N; i++) {
284 default : mx = 0; dx = 0;
break;
291 if (src.
y == dst.
y) {
333 int MaxGroupSize[3];
for(
int i=0; i<3; i++) MaxGroupSize[i]=0;
346 for (
unsigned int i=1; i<a->
outputs(); i++) {
351 if (gsize > MaxGroupSize[gdir]) MaxGroupSize[gdir]=gsize;
358 if (gsize > MaxGroupSize[gdir]) MaxGroupSize[gdir]=gsize;
void collectInternalWires(collector &c)
Draw the internal wires aligning the vertical segments in a symetric way when possible.
void addTrait(const trait &t)
unsigned int outputs() const
const double dWire
distance between two wires
virtual point inputPoint(unsigned int i) const =0
virtual void collectTraits(collector &c)
Draw the two components as well as the internal wires.
void beginPlace(double x, double y, int orientation)
virtual void draw(device &dev)=0
schema * makeParSchema(schema *s1, schema *s2)
virtual void collectTraits(collector &c)=0
unsigned int inputs() const
virtual point inputPoint(unsigned int i) const
The input points are the input points of the first component.
double max(double x, double y)
static int direction(const point &a, const point &b)
Compute the direction of a connection.
static double computeHorzGap(schema *a, schema *b)
Compute the horizontal gap needed to draw the internal wires.
seqSchema(schema *s1, schema *s2, double hgap)
Constructor for a sequential schema (s1:s2).
virtual void draw(device &dev)
Draw the two components as well as the internal wires.
virtual void place(double ox, double oy, int orientation)
Place the two components horizontally with enough space for the connections.
void drawInternalWires(device &dev)
Draw the internal wires aligning the vertical segments in a symetric way when possible.
virtual void place(double x, double y, int orientation)=0
virtual point outputPoint(unsigned int i) const =0
An abstract block diagram schema.
virtual point outputPoint(unsigned int i) const
The output points are the output points of the second component.
schema * makeCableSchema(unsigned int n)
Build n cables in parallel.
schema * makeSeqSchema(schema *s1, schema *s2)
Make a sequential schema.
virtual void trait(double x1, double y1, double x2, double y2)=0