Building makemake

    If you downloaded the link-kit, simply type "Link" to create the binaries.
(I cannot distribute statically linked binaries because that would force me to
place the source under the GPL.)

    The directory containing makemake must be on your execution path in order
for makemake to work correctly.

Changes from previous versions

    With the introduction of version 2.1.0, makedepend is no longer used, so one
no longer has to specify the full path of each source file.  Profiling shows
that version 2.1.0 runs just as fast as the old version that used makedepend,
even though the new version uses dynamic allocation.  Dynamic allocation allows
it to avoid makedepend's hard limits on the number of dependencies.

    Version 2.2.0 adds the tidy target to delete only the .o files.  clean and
tidy are now both double colon targets so you can extend them via extra code in
Make.header.  In addition, both of these targets now use the make variable
${RM}, so they no longer generate error messages if some of the files do not
exist.

makemake

    When compared with the scriptable, integrated development environments
available on other platforms, UNIX make is a painful mess.  makemake was written
to alleviate some of the pain by generating a Makefile from a list of source
files.

    More specifically, given the two files Make.header and Make.files, makemake
parses the files specified in Make.files to calculate their dependency lists and
then generates a Makefile compatible with GNU's version of make.

    Make.header is simply copied to become the first part of the Makefile.  It
should contain all the variable definitions and special targets.  (makemake
automatically generates the targets all, tidy (double colon), clean (double
colon), checksyntax (see makecheck below), touch (see maketouch below), and
jdepend (internal use only).)  In particular, LINKER must be defined to be the
name of the program to use during linking, and DEPENDFLAGS must be set to
contain all the compiler directives so that makedepend will work correctly.
(LINKER is usually just the same as the name of the compiler, but is needs to be
mcc in order to use Mathematica's MathLink package.)

    Here is a simple example of a Make.header file:

    # Useful directories

    MYCODEDIR := .

    # Directories to search for header files

    SEARCHDIRS := -I- -I${MYCODEDIR}

    # makemake variables

    LINKER       := gcc
    DEPENDFLAGS  := -g -Wall -Werror ${SEARCHDIRS}
    TOUCHHEADERS := ${MYCODEDIR}/*.h

    # make variables

    CC       := gcc
    CXX      := g++
    CCC      := g++
    CPPFLAGS  = ${DEPENDFLAGS}

    Make.files contains a simple list of all the files required to build each
target as follows:

    @<name of first target>
    <first object file>
    <second object file>
    ...
    @<name of second target>
    ...

    The object files should not contain a suffix, because makemake appends the
appropriate suffixes automatically.  (e.g. .c, .cc, .o, etc.)  The source file
suffix is .c by default, but can be set with the -suffix option.  The current
suffix can be overridden by placing the desired suffix in front of the source
name as follows:

    -suffix .cc
    @myprog
    .c myprog
    JString

    The first line sets the default suffix to .cc.  The next line specifies the
name of the make target.  The third line tells makemake that the object file
myprog.o is required in order to build myprog, and that the source file is
called myprog.c.  The last line tells makemake that the object file JString.o is
also required in order to build myprog, and that the source file is called
JString.cc.

    makemake correctly calculates dependencies for lex, flex, yacc, and bison
files.  Simply specify the .l or .y suffix.  Dependencies on libraries can be
included by specifying the .a suffix.  Libraries must also be listed in the
standard make variable LOADLIBES so the linker will pick the correct type. (.a
or .so)  Dependencies on precompiled files can also be included by specifying
the .o suffix.  This is useful if some files have to be compiled in a completely
different way, e.g. using a different Makefile.  makemake recognizes both .a and
.o as special suffixes and does not try to calculate their dependencies.

    The -prefix option sets the prefix of all subsequent source files.  This is
useful if a group of files is in a different directory from the Makefile.  For
convenience, the prefix is cleared when a new target is encountered.  As usual,
comments can be included in Make.files by starting the line with a hash (#).

    If no objects files are listed for a target, it is assumed that they are the
same as those for the next target in the file.  This is especially convenient
for building several different versions of the same library.  (e.g. static .a
and shared .so versions)

    The command line options for makemake are as follows:

    -h   prints help
    -hf  <header file name>  - default Make.header
    -if  <project file name> - default Make.files
    -of  <output file name>  - default Makefile
    -c   interactively choose the targets

    The -c option prints a list of the targets found in Make.files, and lets you
choose which ones to include in the final Makefile.  Another way to specify a
particular subset of targets is to include their names after the other options.

    As mentioned above, your own special targets should be included in
Make.header.  Some targets (e.g. TAGS used for the etags program) require a list
of all the source files.  makemake provides this in the variable called
MM_ALL_SOURCES.  Thus, to define the TAGS target, simply include the following
in your Make.header:

    .PHONY : TAGS
    TAGS: ${MM_ALL_SOURCES}
        etags ${MM_ALL_SOURCES} ${TOUCHHEADERS}

makecheck

    Sometimes it is helpful to be able to check a single source file after
modifying it.  This provides instant feedback on typos and such.  Of course, one
would prefer not to have to run make and wait while other files are recompiled
first.  This can be done by running make directly, but one has to include the
path exactly the way it is specified in the Makefile.  makecheck was written to
solve this problem.  Once the Makefile is built, simply type "makecheck
MyClass.cc" to recompile only MyClass.cc.  makecheck finds the correct path for
you.

maketouch

    Sometimes it is necessary to use compile-time flags to include or exclude
certain pieces of code.  (One should obviously try to minimize the need for
this, but NDEBUG, which turns off assert(), will always be there.)  In such
cases, one would prefer not to have to recompile everything (i.e. make clean)
when a flag that only affects a few source files is changed.  maketouch was
written to alleviate this problem.  It works in conjunction with makemake's
special touch target to insure that only the files that use the flag are
actually recompiled.

    Since makemake does most of the work automatically, maketouch is very easy
to use.  First, add a line to Make.header to define TOUCHHEADERS to include the
names of all the header files used in the Makefile.  Generally, this can be done
with something like "/home/jafl/code/myprog/*.h".  Then, after rebuilding the
Makefile, simply type "maketouch compile_flag" to touch all the source and
header files that include "compile_flag".

    For an example of how to define TOUCHHEADERS, refer to the sample
Make.headers given above.