Several functions and variables are to be found in the c file generated by
a cyco run: 

void write_aet_header(void) : writes an aet header to stdio.

void write_aet_frame(int cycle, char *ptr) : writes an aet frame to stdio.  

char *facs[] : list of signals in your model

void sim_comb(void) : simulates combinational logic in the circuit
void sim_latch(void) : simulates the clocked latches in the circuit
void sim_comb_postlatch(void) : simulates combinational logic in the
	circuit that drives output nets.  note that this step may or
	may not be necessary.  if it's not necessary, this function
	will be empty

void sim_front(void) : simulates combinational then latches
void sim_back(void) : simulates latches then combinational
void sim_all(void) : simulates combinational then latches then
	the postlatch combinational logic.

...normally, you'd use sim_all().  i've left this open-ended so you can do
what you need to simulate a model correctly but left the option that users
can select what gets run in what order to speed up simulation by not
having to evaluate some combinational logic nets twice.  

(*) using the -d option will not take "dangling nets" into the backtrace
consideration for postlatch combinational logic.  this option was
added because there's no sense [re]simulating logic that's unused.

there are ways around this with partial simulation of the circuit, but
this will have to do for now.  see the examples directory to see how cyco
was used for the cla-cycle and lines-cycle models.  Cyco now supports
all Ver generated gate types.

-17jan99ajb
