// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module adder168(o, i1, i2);
output [15:0] o;
input [15:0] i1;
input [7:0] i2;
wire [1:16] c;
badd b[0:15]( 
 .ci({1'b0,c[1:15]}),
 .a(i1[0:15]),
 .b({i2[0:7],8'h00}),
 .co(c), 
 .sum(o[0:15])
 );
endmodule