// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module adder82(o, i1, i2);
output [7:0] o;
input [7:0] i1;
input [1:0] i2;
wire [1:8] c;
badd b[0:7] (c,o[0:7],i1[0:7],{i2[0],{7{i2[1]}}},{1'b0,c[1:7]});
endmodule