// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module bsub(co, sum, a,b,ci, zo,zi);
output co,sum,zo;
input a,b,ci,zi;
not #1 (tb,b);
xor #1 (t1,a,tb),
 (sum,t1,ci);
or #2 (co,a&tb,tb&ci,a&ci);
not #1 (zdet,sum);
and #1 (zo,zi,zdet);
endmodule