// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module f0(o, i, m, ck);
input [7:0] i;
input m,ck;
output [7:0] o;
mux1 m[7:0](o,i,{8{m}},{8{ck}});
 
endmodule