// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module f4(o,i1,i2,i3,m3,m2,m1,s,c);
input [7:0] i1,i2,i3;
input m3,m2,m1,s,c;
output [7:0] o;
mx4 m[7:0](o,i1,i2,i3,{8{m3}},{8{m2}},{8{m1}},{8{s}},{8{c}});
endmodule