// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module f5(o,i1,i2,i3,m3,s,c);
input i1;
input [15:0] i2,i3;
input m3,s,c;
output [15:0] o;
mx5a (o[15],i1,i2[15],i3[15],m3,s,c);
mx5b m[14:0] (o[14:0],i2[14:0],i3[14:0],{15{m3}},{15{s}},{15{c}});
endmodule