// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module f7(o, i1, i2, m, s, c);
output [7:0]o;
input m,s,c;
input [7:0] i1;
input [7:0] i2;
mx2 m[7:0](o,i1,i2,{8{m}},{8{s}},{8{c}});
endmodule