// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module killstep(o,i,m,ck);
input ck, m, i;
output [1:0] o;
wire [1:0] o;
wire w;
assign o[0]=1;
assign o[1]=w;
mux1 m1(w,i,m,ck);
endmodule