// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module mx2(o,in1,in2,m,s,ck);
output o;
input in1,in2,m,s,ck;
not #1(t1,s);
not #1(t2,m);
and #1(t3,m,s,in2);
and #1(t4,m,t1,in1);
and #1(t5,t2,o);
or #1 (t6,t3,t4,t5);
dff g02(o,ck,t6);
endmodule