// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module mx3(o,in1,in2,in3, m3, m2, m1, m0, rc15,ck);
output o;
input in1,in2,in3,m3,m2,m1,m0,rc15,ck;
not #1(t1,rc15);
and #1 (t2,m0,in1),
 (t3,m1,in3),
 (t4,m2,in3),
 (t5,m3,rc15,in3),
 (t6,m3,t1,in2);
or #1 (t7,t2,t3,t4,t5,t6);
dff g03(o,ck,t7);
endmodule