// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module package(in1, in2, clk, eoln, mode, xout, yout);
input [7:0] in1;
input [7:0] in2;
input clk;
output eoln;
input [1:0] mode;
output [7:0] xout, yout;
wire [15:0] rc;
wire vectored [15:0] rcr7,rcr8;
wire vectored [1:0] r5bus,r6bus,r5out,r6out;
wire vectored [7:0] x2x1,y2y1,x1out,x1r5,x2out,x1x2,y1y2;
wire vectored [7:0] r7out,r8out,y1out,y2out,y1r6;
assign xout=x1out; 
assign yout=y1out; 
 
and #1(m3, mode[0], mode[1]); 
not #1(mode0bar, mode[0]); 
and #1(m2, mode[1],mode0bar);
not #1(mode1bar, mode[1]); 
and #1(m1, mode1bar, mode[0]);
nor #1(m0, mode[0], mode[1]); 
f3 modx1(x1out, in1, x1r5, x1out, m3, m2, m1, m0, rc[15], clk);
f0 modx2(x2out, in2, m0, clk);
subtractor88 modx2x1(zerox2x1, x2x1, x2out, x1out,cox0),
 modx1x2(zerox1x2, x1x2, x1out, x2out,cox);
adder82 modx1r5(x1r5, x1out, r5bus);
killstep modr5(r5out, cox, m1, clk);
bus modr5bus(r5bus, r5out, eolnbar);
f7 modr7(r7out, x2x1, x1x2, m1, cox, clk);
f4 mody1(y1out, in1, y1r6, y1out, m3, m2, m1, rc[15], clk);
f0 mody2(y2out, in2, m1, clk);
subtractor88 mody2y1(zeroy2y1, y2y1, y2out, y1out,coy0),
 mody1y2(zeroy1y2, y1y2, y1out, y2out,coy);
adder82 mody1r6(y1r6, y1out, r6bus);
killstep modr6(r6out, coy, m2, clk);
bus modr6bus(r6bus, r6out, eolnbar);
f7 modr8(r8out, y2y1, y1y2, m2, coy, clk);
f5 modrc(rc, zerox1x2 , rcr7, rcr8, m3, rc[15], clk);
adder168 modrcr7(rcr7, rc, r7out);
subtractor168 modrcr8(zerorcr8, rcr8, rc, r8out);
not #1 (eolnbar, eoln);
and #1(eoln, zerox1x2, zeroy2y1);
endmodule