// 3612fca4
// Ver: Structural Verilog Compiler v0.99g (w)1998 BSI

library testlib;


module subtractor88(z, o, i1, i2, co);
output z,co;
output [7:0] o;
input [7:0] i1;
input [7:0] i2;
wire [1:8]zer,car;
assign z=zer[8], co=car[8];
bsub b[1:8](car[1:8],o[0:7],i1[0:7],i2[0:7],{1'b1,car[1:7]},zer[1:8],
{1'b1,zer[1:7]});
endmodule