Author: Taketoshi Sano <kgh12351@nifty.ne.jp>
Title: Modeline in XF86Config
$Revision: 1.1.1.1 $, ($Date: 1999/07/15 14:42:16 $)

"Modeline" ԤˤĤơ

XFree86 Ѥ硢˥λͤ˱ơɽ̤
٤ȿ椹뤿 "Modeline" Ԥե
Ǥ XF86Config ˵ܤɬפޤ

 "Modeline" Ԥΰ̣ϡɸ๽ʤ XFree86 Υ֤
ޤޤƤ /usr/X11R6/lib/X11/doc/VideoModes.doc 
ޤޤ man XF86Config ȤƤɤळȤǤޤ

(VideoModes.doc  XF86Config ܸ⤢ޤ
 Ҥ xjman ץȤ˴ؤ򻲾ȤƤ)

"Modeline" Ԥιǡ

XF86Config  "Modeline" Ԥ˽񤫤ƤƤñˤޤȤȡ

  1) Modeline (̥⡼ɤλ)ɤǤ

  2) "name" (⡼̾)  
     ʣΥ⡼ɤ򵭽Ҥݤˤ줾̤뤿̾
     ̾ "800x600" , "640x480" ʤɤβ٤̾դ뤬
     ñˤ狼䤹뤿Ǥäơ "modeA", "modeB"
     ʤɤ̾դƤְ㤤ǤϤޤ

  3) DotClock (ɥåȥå)ǽο͡Ͽ򻲾ȡ

  4) horizontal timing (ʿƱΥߥ) 
     2 ܤ 5 ܤޤǤ 4 Ĥο͡Ͽ򻲾ȡ

  5) vertical timing (ľƱΥߥ)
     6 ܤ 9 ܤޤǤ 4 Ĥο͡Ͽ򻲾ȡ

  6) Flags (եå)٤ưλꡣ man XF86Config

 6 ĤʬǤޤˤäƤ HSkew Ȥ 7 ܤ
ܤɬפˤʤ餷ǤۤȤɸȤ̵Τǡ
ˤĤƤϾάޤ

 1) ϥɤʤΤѹǤʤ 2) λˤĤƤ
ˤʤ뤳ȤϤޤ̵Ǥ礦ޤ 6) ˤĤƤȤꤢ
֤Ƥޤ礦

Ǥϡ 3), 4), 5) οͤɤäƷ٤
ȤˤĤƹͤƤߤޤ 

(줾οͤλỊ̇ˤĤƤϿ A 򻲾ȤƤ
 ޤŪʿͤˤĤƤϸҤ򻲹ͤˤƤ)

֥ɥåȥåƱߥ󥰡

ޤʬȤ˥λͤ顢ʿӿľƱȿ
˥ӥǥӰͤϤ狼äƤΤȤޤ
ޤꤷ̲ (ʿ / ľ) ޤäƤΤ
ޤ

(Ѹΰ̣Ͼ嵭 VideoModes.doc 򻲾ȤƲ)



 ˥ (CRT/LCD) οʿƱȿ MHsync
 ˥ (CRT/LCD) οľƱȿ MVsync
 ˥ (CRT/LCD) ΥӥǥӰ: MVB

 ꤷ̲ (ʿ) : Hres
 ꤷ̲ (ľ) : Vres

ɽޤ

 "Modeline" Ԥǻꤹ٤ͤ

Modeline "modeA" clockval Hres HsyncS HsyncE HFL Vres VsyncS VsyncE VFL

ȤɽޤƤ狼褦ˡ "Modeline" Ԥǻꤹͤ
 2 Ľϡꤷ̲٤򤽤Τޤ޻ꤷޤ

ơˤ뤳Ȥ HFL, clockval, VFL 뤳ȤǤ

ȤꤢͤȤơ Hres  1.25 ׻줿ͤ
äȤᤤ 8 ܿ˴ݤ HFL ȤޤȤơ

 ֥ɥåȥåסֿʿɥåȿĤޤʿե졼Ĺ
  ֥ӥǥɤϤʿĤޤʿƱȿ

Ȥط (ӥǥɤѤʿƱȿȥ˥
οʿƱȿȤΰ̣ΰ㤤İƤƲ) 
ɥåȥåοͤ

  clockval [MHz] = MHsync [kHz]  HFL (ɥåȿ)  1000 (ñ̴)

ꤷޤǤޤ

 clockval < MVB (˥λͤˤ)

 clockval < [Maximum allowed dotclock] (ӥǥɤˤ)

ǧƤƤ

ˡ

 ֥ɥåȥåסֿʿɥåȿĤޤʿե졼Ĺ
  ֿľɥåȿĤޤľե졼Ĺ
  ֥ӥǥɤϤľĤޤľƱȿ

Ȥط (ǤӥǥɤѤľƱȿ
˥;οľƱȿȤΰ̣ΰ㤤İƤƲ)
 VFL οͤ

  VFL = clockval [MHz]  HFL (ɥåȿ)  Vsync [kHz]  1000 (ñ̴)

Ȥޤڤ夲ˤƲ
 8 ܿ˴ݤɬפϤޤ

  
      μǤ狼Ȥꡢ HFL ѹˤϡѹ HFL 
      碌 VFL ׻ľɬפޤդƲ

ǡ VFL > (Vres  1.05) ˤʤäƤ dotclock, HFL, VFL 
ͤȤƤϽʬǤȤϤȤꤢ

 HsyncS = Hres + ( (HFL - Hres)  3 )
 HsyncE = HFL  - ( (HFL - Hres)  3 )

 VsyncS = Vres + ( (VFL - Vres)  3 )
 VsyncE = VFL  - ( (VFL - Vres)  3 )

ȤǤ⤷Ƥޤ礦(ͤϤ٤ˤʤ褦ڤ夲Ʋ)
¤Ϥ 4 ĤοͤηϤʤꤤøǤ֤󤳤Ǥ
Ȥ֤ɽʤǤ礦äɤ׻ƤǤ
ͤϢƲ

ǤϲΤΤ褦ʤøʷ򤳤˽񤤤Ƥ뤫Ȥȡ
 "xvidtune" Ȥʥġ뤬뤫Ǥ

 4 Ĥο (HsyncS, HsyncE, VsyncS, VsyncE) ϲϿ
ñƤޤʿľ줾ΡƱ泫ϰ֡
Ʊ潪λ֡פ򼨤ޤοͤɽ̤ΰ
礭ƶޤ

̤˥Ƥ硢ʿƱΰ (horizontal timing 
 2 Ĥο)  8 ܿ䤷ޤդξϸ餷ޤ
˥ƤϡľƱΰ (vertical timing  
2 Ĥο) 򤹤餷ޤ(ľ 8 ܿǤʤƤɤ) 
դξ䤷ޤ

ºݤˤϡ֤ĴɽĴϥǥǥ⡼ɥ饤
ͤԽʤԺꡢ xvidtune ȤġȤäۤ
äǴñǤΥġǺŬʥ⡼ɥ饤򸫤ĤƤοͤ
⤷Ƥ 1 ⡼ɥ饤ԽɤΤǤ
٤ X Ƶưꤹ֤ʤޤ

ȤȤǡȤꤢ dotclock, Hres, HFL, Vres, VFL ˤĤ
ʽͤСȤ xvidtune Ĵ뤳
Ǥʤ "Modeline" ԤФϤǤ
ʬȤäƤϡɥ˹碌 "Modeline" Ԥʬ
׻ƺäƤߤƲ

  :
  ʤȤ 3.3 ʹߤ XF86_SVGA  C&T ɥ饤СǤ
  ץ "use_modeline" ȤäŪ˻ꤷʤϡ
   "ModeLine" Ԥǻꤵ줿ͤΤ 3)  DotClock 
  Ȥʳ 4), 5) ǻꤵ줿ͤϻȤޤ
   (ȤꤢϤʤȥޥǤܺ٤ XFree86 
    ɥȤǤ README.chips ɤǲ)

  :
  ºݤ˿ͤä ModeLine Υץ뤬ߤͤϡ XFree86 
  °ʸǤ /usr/X11R6/lib/X11/doc/Monitors 򸫤Ƥߤ
  ɤǤ礦 XF86Config ǻꤹ Monitor Ƥ
  ˥ε̤¤Ǥޤ


Ͽ A: ɥåȥåƱߥ󥰤ˤĤƤ

嵭 3) DotClock, 4) horizontal timing, 5) vertical timing
Τ줾ˤĤơ⤦ܤȰʲΤ褦ˤʤޤ

3) DotClock ӥǥɤϤ椬 1 ô֤
   ɤΥɥå (1 )  () Ǥ뤫
   ɽȿ (ɥåȥå / DotClock)
   XF86Config Ǥñ̤ MHz (ᥬإ)

    :
    ˥¤С̩ˤϡ֥ɥå (ȯ)
    ȡֲ (̾ΰ֤򼨤Ǿñ)פƱ̣ĤΤ
    Υ˥ξǤꡢ R/G/B  3 ĤΡ֥ɥåȡפ
    ҤȤĤΡֲǡפ륫顼˥ξˤϥɥåȤ
    Ǥ̤γǰˤʤޤ

     XFree86 Ȥ硢㤨 C&T ɥ饤ФǤ LCD  CRT 
    Ʊɽˤθơ  XF86Config Ǥϡ֥ɥåȡפ
    ֲǡפƱ̣ĤȤƹͤƤۤʤ褦
    Ƥޤܺ٤ϼ򻲾ȤΤȡ

   ʤǶΥɤξϥץޥ֥륯åͥ졼
   Ȥ뤳Ȥ¿ΤǤξˤϺǽ˵󤲤
   Ӱ (Maximum allowed dot-clock: ǹƥɥåȥå) 
   㤤Ǥդμȿư뤳ȤǤޤ

   ΡӰפϡ㤨 XFree86  XF86_SVGA Фå

   (--) SVGA: Maximum allowed dot-clock: 135.000 MHz

   ȤԤǼƤޤ

   :
      վǥץ쥤 (LCD) ȤäΡȥޥξ硢
      ӥǥåפФƥӥǥ꤫ LCD ؤžå
      Ϳ뤳Ȥޤξץह٤ʤΤϥɥåñ
      ΥåǤ

      ȤС8 bpp16 bpp24 bpp 򤽤줾Ʊ졼
      ɽ褦ȤС16 bpp Ǥ 8 bpp λܡ24 bpp Ǥ
      3 ܤΥåͿɬפޤ

      LCD  CRT ؤΡ֥ɥåȥåפ򤽤Τޤ
      DAC ͳ CRT ͿȥСå CRT ɽǤ
      äˤʤ뤳Ȥޤ褹뤿ᡢC&T ɥ饤
      Ǥϻꤵ줿å˥ԥ뤢ΥХȿ褸 LCD 
      ȤݤΥžåȤƤޤ
      ˤꡢLCD  CRT ˰ĤΥ⡼ɥ饤бǤˤʤޤ
      (ܺ٤ϥɤǧƤ)

      Ƕ XFree86 ǤʣΥ⡼ɥ饤󤬻Ȥ뤫⤷ʤΤǡ
      ͤʹפɬפʤ⤷ޤ󡣤Τ⥰եå
      ɥ饤Сˤäưۤʤǽ뤿ᥳɤγǧɬפǤ

4) horizontal timing : ǽοͤɽʬοʿΥɥåȿ
    (ʿ) 2 ܤοͤϿʿƱγϥɥåȡ 
    3 ܤοͤϿʿƱνλɥåȡ 4 ܤοͤɽ
    (Ʊޤ)碌ʿɥåȿǤ
    4 ܤοֿͤʿե졼ĹפȸƤӤޤοʿ 4 Ĥ
   ͤϤ٤ 8 ܿˤƤɬפޤ

   :
      XFree86-Video-Timing-HOWTO ˤȡǡ 8 ܿפˤ
      Τϡ 8 ӥåȥ쥸 3 ӥåȤ餷 11 ӥåȤ
      ͤ褦 SVGA  S3  VGA ֤ˤͭפ
      ǤϡɥˤäƤ 8 ܿˤɬפ̵
      ʤǤǧ at your own risk Ǥɤ

    horizontal timing δطޤˤȡΤ褦ˤʤޤ

                    |<-------------- HFL -------------->|
     HD   ------+   +-------------------------------+   +---------
                |   |                               |   |
                ~~~~~                               ~~~~~
                hsync                               hsync

     DENA --+          +------------------------+          +------
            |          |                        |          |
            ~~~~~~~~~~~                         ~~~~~~~~~~~
                    |<>|<--------- HR --------->|<->|   |<>|
                    HBP                         HFP HSP HBP|
                       |<-------------- HFL -------------->|


                 1.    |----------------------->| HR
                 2.    |--------------------------->| HR+HFP
                 3.    |------------------------------->| HFL-HBP
                 4.    |---------------------------------->| HFL

   

    HR (Horizontal Resolution) : 
       ɽʬοʿΥɥåȿ (ʿ)

    HSP or hsync (Horizontal Sync) : ʿƱ

    HFP (Horizontal frontporch) : եȥݡ
       ɽνλʿƱ (hsync) γϤޤǡ

    HBP (Horizontal Backporch) : Хåݡ
       ʿƱ (hsync) λƤɽγ
       ( HFL γ) ޤǡ

    HFL (Horizontal Frame Length) ʿե졼Ĺ
       ɽ (Ʊޤ) 碌ʿɥåȿ

     ǽפʤȤϡ֥ɥåȥåʿե졼Ĺǳä
     ͤ˥λͤ˵ܤ줿ʿƱȿ¤ĶƤϤʤ
     ȤȤǤ

     ޤޥ󥯥˥Ǥʤ (Ʊȿξ)
     ֥ɥåȥåʿե졼Ĺǳäͤ˥
     ͤˤʿƱȿȤۤƱǤʤȤ줤ɽʤ
     ȤȤФƤɬפޤʤߤ¢ LCD ξ
      XF86Config 硢̾ƱȿȤƹͤƤ
     ɤǤ礦 
     (ʥ³γդ LCD ǤϥޥбΤΤ⤢ޤ)

5) vertical timing : "horizontal timing" Ʊͤˡǽοͤɽʬ
   οľ饤 (ľ) 2 ܤοͤϿľƱγϥ饤
   3 ܤοͤϿľƱνλ饤 4 ܤοͤɽ
   (Ʊޤ)碌ľ饤Ǥ
   4 ܤοֿͤľե졼ĹפȸƤӤޤ

    vertical timing ˤĤƤ⡢ horizontal timing Ʊͤˡ
   οޤΤ褦ˤʤޤ

                    |<-------------- VFL -------------->|
     VD   ------+   +-------------------------------+   +---------
                |   |                               |   |
                ~~~~~                               ~~~~~
                vsync                              vsync

     DENA --+          +------------------------+          +------
            |          |                        |          |
            ~~~~~~~~~~~                         ~~~~~~~~~~~
                    |<>|<--------- VR --------->|<->|   |<>|
                    VBP                         VFP VSP VBP|
                       |<-------------- VFL -------------->|

                 1.    |----------------------->| VR
                 2.    |--------------------------->| VR+VFP
                 3.    |------------------------------->| VFL-VBP
                 4.    |---------------------------------->| VFL

   

    VR (Vertical Resolution) : 
       ɽʬοľΥɥåȿ (ľ)

    VSP or vsync (Vertical Sync) : ľƱ

    VFP (Vertical frontporch) : եȥݡ
       ɽνλľƱ (vsync) γϤޤǡ

    VBP (Vertical backporch) : Хåݡ
       ľƱ (vsync) λƤɽγ
       ( VFL γ) ޤǡ

    VFL (Vertical Frame Length) ľե졼Ĺ
       ɽ (Ʊޤ) 碌ľɥåȿ

     ȤǿľƱȿʿƱδطϡޤΤ褦˼ȤǤޤ

                     |<-------------- VFL -------------->|
      VD   ------+   +-------------------------------+   +---------
                 |   |                               |   |
                 ~~~~~                               ~~~~~
                        HFL
      DENA +++          ++++++++++++++++++++++++++          +++++++
           |||          ||||||||||||||||||||||||||          |||||||
             ~~~~~~~~~~~                         ~~~~~~~~~~~
     
     DENAκ٤δ֤1 ʿ (HFL) ˤʤޤ
      VFL ˤȡ HFL ϶ˤû֤ʤΤǡ
     Ʊ˸Ƥޤޤ

Ͽ B: 

  (ʲξϾľ (ogiso@use-net.co.jp) 󤫤
   󶡤줿ΤǤ)

   Q:
      Toshiba TECRA 720CT, XFree86 Version 3.3.3 δĶ
      XF86_SVGA server Ȥä 1024x768 pixel, 16bpp 
      ɽǤޤ

   A: 
      ǽ XF86Setup ˤѹ
      ǥˤ XF86Config եԽʤɤ
      ˡˤä

Option "fast_dram" 
Set_MemClk 38.000

ꤷƲ

 memory clock ʰʲ MomoryClkˤ default ͤ
®뤿Ǥˤä Maximum allowed dot-clock
(ʲ Max Dotclock) 礭ʤ Modeline  DotClock ͤ
礭뤳ȤǤޤ
Max DotclockMaxDClkMemoryClk δطˤĤƤ
/usr/X11R6/lib/X11/doc ˤ README.chips 

5. The Full Story on Clock Limitations



TECRA 720CT ȤäƤåפ CT65550 (5V) Ǥꡢ
嵭ʸˤȤΥåפλͤ

MaxDClk = 110 
MemoryClk = 38 

ȤʤäƤ뤿 "Set_MemClk 38.000" Ȥޤ

ޤξϤˤ 16bpp Ǥ Max Dotclock  53.2 
񤫤Ƥޤº X ưƤߤ

Maximum allowed dot-clock: 53.197 MHz

ȤʤäƤޤ嵭 5 Ϥη׻򸫤ʬޤ

ơ

Modeline  DotClock < Max Dotclock

ǤʤФʤޤ󡣤礭ͤꤹ

(--) SVGA: Clock for mode "1024x768" is too high for the configured hardware.
           Limit is  53.197 MHz

Ȥʤ X ưǤʤʤޤ DotClock = 53 Ȥ

Modeline  "1024x768"   53.00 1024 1032 1176 1344 768 771 777 806

ꤹɤǤ礦ΤޤޤǤ

Fatal server error:
No valid modes found.

Ȥʤä X ưǤʤȤޤ
 HorizSync  VertRefres 뤳Ȥ

HorizSync       30-69
VertRefresh     40-87

ꤹ뤳Ȥǲ褷ޤ
κͤߤ礭뤳ȤϤǤޤ
ʤ

DotClock < Maximum Video Bandwidth (MVB)

ǧ HorizSync  VertRefres κ
դɬפϤʤʤΤǤ

http://www.csd.toshiba.com/tais/csd/support/files/

ʤɤΥڥåɽ򸫤Ƥ LCD ΥӥǥӰˤĤ
ϺܤäƤޤΤǡ URL  
Tecra 720 CDT Video Mode Information ˵ҤƤ 
Vertical Refresh Rate  Horizontal Refresh Rate κͤ
ꤷƤޤ

ˤդ DotClock ꤷȤˤ LCD »
ɤݸȤʤޤ CRT ȤξϤ CRT  MVB 
¸ޤΤǤθ¤ǤϤޤ

ޤʤȤ 3.3 ʹߤXF86_SVGA  C&T ɥ饤СǤ

Option  "use_modeline"

ȤäŪ˻ꤷʤϡ"ModeLine" Ԥǻꤵ줿ͤΤ
 DotClock ȤʳοͤϻȤޤ

ä DotClock ʲϤޤ굤ˤʤƤɤǤ
ŬͤꤷʤФʤޤ

ּռ

ʸϡ XFree86-Video-Timings-HOWTO ١Ȥ
鼫ʬΤꤿäȤȴФȤտޤ
ޤꥸʥʸ줿 ESR ᡢޤ
ܸ줿ܰ칬˼հդɽޤ

ʸ˴ޤޤޤ Laptop-X-ml ˤᤤ᤬Ƥ줿
ƤĺΤǤѤĤĺޤʸƤ
ĤƤ⤤ȥɥХ򤷤Ʋäᤤ˼հդ
ɽޤ

ºݤˤʸȤäƤߤи顢 եɥХå
äľˤհդɽޤˤä
­Ƥ䤦ȤǤޤ

ơ XFree86 ˽ޤäƥСγȯ˹׸Ƥ볫ȯԤ
ä˻䤬äˤʤäƤ David Bateman ϤȤ
C&T ɥ饤СγȯԤˤհդɽޤ
餬ʤС䤬ʸ뤳Ȥ̵äǤ礦

ֻ͡

 1999 ǯ 5 ˸줿 xjman-0.3 ˤϡ XF86Config  man page 
ޤ 6 ˸줿 xjdoc-0.3 ˤ XFree86 ver 3.3.3.1 б
VidModes (XFree86-Video-Timings-HOWTO) ܸޤޤƤޤ

ޤ¥꡼ǤʤΩĤϤǤΤѲ 
(Ƥ˴ؤƤθոХեɥХå򤪴ꤤޤ)
۾ϼΤȤǤ

 <http://xjman.dsl.gr.jp/xjman-0.3.tar.gz> ( 1 MB)
 <http://xjman.dsl.gr.jp/xjdoc-0.3.tar.gz> ( 500KB)

ʤ xjman-0.3 ˤĤƤϼ FreeBSD 桼Τ ports 
ޤ Debian 桼Τ .deb package 줾Ƥޤ

